Integrated circuit packaging system with exposed conductor and method of manufacture thereof
AssigneeSTATS ChipPAC, Ltd.
InventorsDeokKyung Yang, SeungYun Ahn
Life of this patent
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Abstract
A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a component connector on the substrate; forming a resist layer on the substrate with the component connector exposed; forming a vertical insertion cavity in the resist layer, the vertical insertion cavity isolated from the component connector or a further vertical insertion cavity, the vertical insertion cavity having a cavity side that is orthogonal to the substrate; forming a rounded interconnect in the vertical insertion cavity, the rounded interconnect nonconformal to the vertical insertion cavity; and mounting an integrated circuit device on the component connector.
Claims20
A method of manufacture of an integrated circuit packaging system comprising:
- providing a substrate;
- forming a component connector on the substrate;
- forming a resist layer on the substrate with the component connector exposed;
- forming a vertical insertion cavity in the resist layer, the vertical insertion cavity isolated from the component connector or a further vertical insertion cavity, the vertical insertion cavity having a cavity side that is orthogonal to the substrate;
- forming a rounded interconnect adhered to the cavity side in the vertical insertion cavity and providing a cavity gap exposing the substrate between portions of the rounded interconnect opposite to and not in contact with the cavity side and the cavity side;
- and
- mounting an integrated circuit device on the component connector.
A method of manufacture of an integrated circuit packaging system comprising:
- providing a substrate;
- forming a component connector on the substrate;
- forming a resist layer on the substrate with the component connector exposed;
- forming a vertical insertion cavity in the resist layer, the vertical insertion cavity having sides orthogonal to the substrate and isolated from the component connector or a further vertical insertion cavity, the vertical insertion cavity having a cavity side that is orthogonal to the substrate;
- forming a rounded interconnect adhered to the cavity side in the vertical insertion cavity and providing a cavity gap exposing the substrate between portions of the rounded interconnect opposite to and not in contact with the cavity side and the cavity side;
- and
- mounting an integrated circuit device on the component connector adjacent the vertical insertion cavity.
An integrated circuit packaging system comprising:
- a substrate;
- a component connector on the substrate;
- a resist layer having a vertical insertion cavity on the substrate, the component connector exposed from the resist layer, the vertical insertion cavity isolated from the component connector or a further vertical insertion cavity, the vertical insertion cavity having a cavity side that is orthogonal to the substrate;
- a rounded interconnect adhered to the cavity side in the vertical insertion cavity and to provide a cavity gap between portions of the rounded interconnect opposite to and not in contact with the cavity side and the cavity side;
- and
- an integrated circuit device on the component connector.
Dependencies are inferred from the claim text.