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US 2011/0210413 A1Published application
Chip package and fabrication method thereof
OwnerYu-Lung HUANG, Tsang-Yu Liuinventors
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Abstract
An embodiment of the invention provides a chip package, which includes: a semiconductor substrate having a device region; a package layer disposed on the semiconductor substrate; a spacing layer disposed between the semiconductor substrate and the package layer and surrounding the device region; and an auxiliary pattern having a hollow pattern formed in the spacing layer, a material pattern located between the spacing layer and the device region, or combinations thereof.
Claims24
A chip package, comprising:
- a semiconductor substrate having a device region;
- a package layer disposed on the semiconductor substrate;
- a spacing layer disposed between the semiconductor substrate and the package layer and surrounding the device region;
- and
- an auxiliary pattern comprising a hollow pattern formed in the spacing layer, a material pattern located between the spacing layer and the device region, or combinations thereof.
2 more elements
A method for fabricating a chip package, comprising:
- providing a package layer;
- forming a spacing material coating on the package layer;
- patterning the spacing material coating to form a spacing layer and an auxiliary pattern;
- providing a semiconductor wafer comprising a plurality of device regions and scribe lines between any two neighboring device regions;
- bonding the package layer to the semiconductor wafer, wherein the spacing layer surrounds the device region of the semiconductor wafer, and the auxiliary pattern comprises a hollow pattern formed in the spacing layer, a hollow pattern located on the scribe lines, a material pattern located between the spacing layer and the device region, or combinations thereof;
- and
- cutting the semiconductor wafer along the scribe lines to form a plurality of chip packages.
4 more elements
Dependencies are inferred from the claim text.