Devices with nanocrystals and methods of formation

A method of forming a floating gate transistor, comprising:

• forming at least one pair of isolated diffused regions having a first doping type and a first doping level in a top surface of a substrate having a second doping type and a second doping level, wherein a length between the two isolated diffused regions is approximately 40 nanometers and a width of the region between the two isolated diffused regions is approximately 40 nanometers forming a 40 by 40 nanometer channel region;
• forming a gate dielectric having a first thickness disposed above the top surface of the substrate at least between the pair of isolated diffusions;
• forming a plurality of isolated nucleation sites in the gate dielectric;
• forming isolated nanocrystals on a top surface of the gate dielectric with a substantially even statistical distribution across the channel region;
• forming an inter-gate dielectric having a second thickness disposed over the plurality of nanocrystals;
• and
• forming a control gate electrode disposed over the inter-gate dielectric.

A method of forming a floating gate transistor, comprising:

• forming at least one pair of isolated diffused regions having a first doping type and a first doping level in a top surface of a substrate having a second doping type and a second doping level;
• forming a gate dielectric having a first thickness disposed above the top surface of the substrate at least between the pair of isolated diffusions;
• performing ion implantation to form a plurality of isolated nucleation sites in the gate dielectric;
• forming a plurality of isolated nanocrystals on a top surface of the gate dielectric;
• forming an inter-gate dielectric having a second thickness disposed over the plurality of nanocrystals;
• and
• forming a control gate electrode disposed over the inter-gate dielectric.

A non-volatile transistor, comprising:

• a semiconductor substrate having at least two diffused regions with a diffusion type opposite of the substrate forming a source region and a drain region;
• a channel region disposed between the source and drain;
• a dielectric layer disposed above the channel region;
• a plurality of electrically isolated nanocrystals having a maximum diameter of 4.0 nanometers and a density of greater than one nanocrystal per 20 square nanometers disposed upon the dielectric layer;
• an inter-gate dielectric layer disposed above the nanocrystals;
• and
• a control gate electrode disposed upon the inter-gate dielectric layer.

A flash memory, comprising:

• a semiconductor substrate having a plurality of pairs of diffused regions forming source/drain pairs;
• a channel region disposed between each of the source/drain pairs;
• a dielectric layer disposed above the channel region;
• a plurality of electrically isolated nanocrystals having a maximum diameter of 4.0 nanometers and a density of greater than one nanocrystal per 20 square nanometers disposed upon the dielectric layer;
• an inter-gate dielectric layer disposed above the nanocrystals;
• a plurality of control gate electrode disposed upon the inter-gate dielectric layer above the channel regions;
• and
• conductive signal lines interconnecting the plurality of control gate electrodes.