High electron mobility transistor, epitaxial wafer, and method of fabricating high electron mobility transistor

An epitaxial substrate for a high electron mobility transistor, the epitaxial substrate comprising:

• a free-standing substrate having a III nitride region;
• a first III nitride barrier layer provided on the III nitride region;
• and
• a III nitride channel layer provided on the first III nitride barrier layer,
• a first surface of the III nitride channel layer forming a first heterojunction with the first III nitride barrier layer,
• the III nitride channel layer including compressive internal strain such that a piezoelectric field of the III nitride channel layer is oriented in a direction the substrate towards the first III nitride barrier layer,
• a primary surface of the supporting base extending along a plane, the plane having a normal axis inclined at an inclination angle in a range of 40 degrees to 85 degrees or 140 degrees to 180 degrees with respect to a c-axis of the first III nitride barrier layer,
• the first heterojunction extending along a plane, the plane having a normal axis inclined at an inclination angle in a range of 40 degrees to 85 degrees or 140 degrees to 180 degrees with respect to a c-axis of the III nitride region,
• a second surface of the III nitride channel layer extending along a plane, the plane having a normal axis inclined at an inclination angle in a range of 40 degrees to 85 degrees or 140 degrees to 180 degrees with respect to a c-axis of the first III nitride barrier layer, and
• the second surface of the III nitride channel layer being opposite to the first surface of the III nitride channel layer.

A method of fabricating a high electron mobility transistor, the method comprising the steps of:

• preparing a free-standing substrate, the free-standing substrate including a III nitride region;
• growing a first III nitride barrier layer on the III nitride region;
• growing a III nitride channel layer on the first III nitride barrier layer;
• and
• forming a gate electrode on the III nitride channel layer, the gate electrode being configured to exert an electric field on the first heterojunction,
• the III nitride channel layer including compressive internal strain such that a piezoelectric field in the III nitride channel layer is oriented in a direction from the supporting base towards the first III nitride barrier layer,
• the III nitride channel layer forming a first heterojunction with the first III nitride barrier layer,
• a primary surface of the substrate extending along a plane, the plane having a normal axis inclined at an inclination angle in a range of 40 degrees to 85 degrees or 140 degrees to 180 degrees with respect to a c-axis of the III nitride region, and
• the first heterojunction extending along a plane, the plane having a normal axis inclined at an inclination angle in a range of 40 degrees to 85 degrees or 140 degrees to 180 degrees with respect to the c-axis of the III nitride region.