Tri-Gate Field-Effect Transistors Formed by Aspect Ratio Trapping
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorAnthony J. Lochtefeld
Life of this patent
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Abstract
Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of the crystalline material and defining a gate thereover. Defects are reduced by using an aspect ratio trapping approach
Claims20
A semiconductor structure comprising:
- a semiconductor fin on a substrate, the substrate comprising a first crystalline semiconductor material, the semiconductor fin comprising a second crystalline semiconductor material, the second crystalline semiconductor material being lattice-mismatched to the first crystalline semiconductor material, the second crystalline semiconductor material adjoining the first crystalline semiconductor material at an interface, the interface having a rectangular area, the rectangular area having a width and a length, the length being greater than or equal to the width, the semiconductor fin comprising a sidewall extending from the interface to a height above the interface, the height being greater than half the width, and a majority of dislocation defects in the second crystalline semiconductor material terminate at or below the height;
- and
- a gate on the sidewall of the semiconductor fin and on a top surface of the semiconductor fin.
A method for forming a semiconductor structure, the method comprising:
- epitaxially growing a semiconductor fin on a semiconductor substrate, the semiconductor substrate comprising a first crystalline semiconductor material, the semiconductor fin being at least partially disposed in a trench in a dielectric layer on the semiconductor substrate, the trench having a height and a width, the height being greater than or equal to half the width, the semiconductor fin comprising a second crystalline semiconductor material lattice-mismatched from the first crystalline semiconductor material, the second crystalline semiconductor material adjoining the first crystalline semiconductor material, a majority of dislocation defects in the second crystalline semiconductor material terminating within the trench;
- removing a portion of the dielectric layer to expose a sidewall of the semiconductor fin;
- and
- forming a gate on the sidewall of the semiconductor fin and over a top of the semiconductor fin.
A method for forming a semiconductor structure, the method comprising:
- forming a substrate fin on a semiconductor substrate, the substrate fin being integral to the semiconductor substrate, the substrate fin having a width and a length at a base, the semiconductor substrate comprising a first crystalline semiconductor material;
- forming a dielectric layer on the semiconductor substrate;
- planarizing a top surface of the dielectric layer and the substrate fin;
- removing at least a portion of the substrate fin to define a trench, the trench having a height, the height of the trench being equal to or greater than half of the width of the substrate fin;
- forming, in the trench, a second material layer comprising a second crystalline semiconductor material having a lattice mismatch with the first crystalline semiconductor material, a majority of dislocation defects in the second crystalline semiconductor material terminating within the trench;
- removing a portion of the dielectric layer to expose a side portion of the second material layer;
- and
- defining a gate over the second material layer.
Dependencies are inferred from the claim text.