Semiconductor device

A semiconductor device comprising:

• a memory cell comprising:
• a first transistor comprising a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region wherein the first transistor has a positive threshold voltage;
• a second transistor comprising a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region wherein the second channel formation region has a different semiconductor material from the first channel formation region and has an energy gap of greater than 3 eV;
• and
• a capacitor including a first electrode and a second electrode,
• a source line electrically connected to the first source electrode;
• a bit line electrically connected to the first drain electrode,
• a first signal line electrically connected to the second source electrode,
• a second signal line electrically connected to the second gate electrode, and
• a word line electrically connected to the first electrode of the capacitor,
• wherein the first gate electrode, the second drain electrode and the second electrode of the capacitor are electrically connected to each other to form a node for holding charge.

A semiconductor device comprising:

• a memory cell comprising:
• a first transistor comprising a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region wherein the first transistor has a positive threshold voltage;
• an insulating layer formed over at least a part of the first transistor;
• a second transistor over the insulating layer, the second transistor comprising a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region wherein the second channel formation region has a different semiconductor material from the first channel formation region and has a band gap of greater than 3 eV, and wherein one of the second source electrode is in contact with an upper surface of the first gate electrode,
• wherein the first gate electrode and the second drain electrode are electrically connected to each other to form a node for holding charge.

A driving method of a semiconductor device comprising a plurality of memory cells, each comprising:

• a first transistor comprising a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region wherein the first transistor has a positive threshold voltage;
• a second transistor comprising a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region wherein the second channel formation region has a different semiconductor material from the first channel formation region;
• and
• a capacitor including a first electrode and a second electrode,
• a source line electrically connected to the first source electrode;
• a bit line electrically connected to the first drain electrode,
• a first signal line electrically connected to the second source electrode,
• a second signal line electrically connected to the second gate electrode, and
• a word line electrically connected to the first electrode of the capacitor,
• wherein the first gate electrode, the second drain electrode and the second electrode of the capacitor are electrically connected to each other to form a node for holding charge, the driving method comprising:
• applying a positive voltage to one of the word lines for reading data of the memory cells associated with the one of the word lines during a first period;
• and
• applying a zero voltage to remainder of the word lines during the first period.