Semiconductor device and manufacturing method thereof

A semiconductor device comprising a circuit, the circuit comprising:

• a first transistor;
• a second transistor;
• a third transistor;
• a fourth transistor;
• a fifth transistor;
• a sixth transistor;
• a seventh transistor;
• and
• an eighth transistor,
• wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,
• wherein one of a source and a drain of the second transistor is electrically connected to a second wiring,
• wherein the other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the second transistor,
• wherein one of a source and a drain of the third transistor is electrically connected to a third wiring,
• wherein one of a source and a drain of the fourth transistor is electrically connected to the second wiring,
• wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the second transistor,
• wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the second transistor,
• wherein a gate of the third transistor is electrically connected to the one of the source and the drain of the third transistor,
• wherein a gate of the fourth transistor is electrically connected to a gate of the first transistor,
• wherein one of a source and a drain of the fifth transistor is electrically connected to the third wiring,
• wherein one of a source and a drain of the sixth transistor is electrically connected to the second wiring,
• wherein the other of the source and the drain of the fifth transistor is electrically connected to the other of the source and the drain of the sixth transistor,
• wherein a gate of the sixth transistor is electrically connected to the gate of the second transistor,
• wherein one of a source and a drain of the seventh transistor is electrically connected to the second wiring,
• wherein the other of the source and the drain of the seventh transistor is electrically connected to the gate of the first transistor,
• wherein one of a source and a drain of the eighth transistor is electrically connected to the second wiring,
• wherein the other of the source and the drain of the eighth transistor is electrically connected to the gate of the second transistor, and
• wherein a gate of the eighth transistor is electrically connected to a gate of the fifth transistor,
• wherein each of the first, second, third, fourth, fifth, sixth, seventh and eighth transistors comprises an oxide semiconductor layer having a channel formation region, the oxide semiconductor layer comprising an In—Sn—Zn—O based semiconductor.

A semiconductor device comprising an inverter circuit, the inverter circuit comprising:

• a first transistor;
• a second transistor;
• wherein a source of the first transistor is electrically connected to a drain of the second transistor;
• wherein a gate of the first transistor is electrically connected to the source of the first transistor, and
• wherein each of the first transistor and the second transistor comprises an oxide semiconductor layer having a channel formation region, the oxide semiconductor layer comprising an In—Sn—Zn—O based semiconductor.

A semiconductor device comprising an inverter circuit, the inverter circuit comprising:

• a first transistor;
• and
• a second transistor;
• wherein a source of the first transistor is electrically connected to a drain of the second transistor;
• wherein a gate of the first transistor is electrically connected to a drain of the first transistor, and
• wherein each of the first transistor and the second transistor comprises an oxide semiconductor layer having a channel formation region, the oxide semiconductor layer comprising an In—Sn—Zn—O based semiconductor.

A semiconductor device comprising a circuit, the circuit comprising:

• a first transistor;
• a second transistor;
• a third transistor;
• and
• a fourth transistor,
• wherein one of a source and a drain of the first transistor is electrically connectable to a first terminal of a driver IC,
• wherein one of a source and a drain of the second transistor is electrically connectable to the first terminal of the driver IC,
• wherein one of a source and a drain of the third transistor is electrically connectable to a second terminal of the driver IC,
• wherein one of a source and a drain of the fourth transistor is electrically connectable to the second terminal of the driver IC,
• wherein the other of the source and the drain of the first transistor is electrically connected to a first signal line,
• wherein the other of the source and the drain of the second transistor is electrically connected to a second signal line,
• wherein the other of the source and the drain of the third transistor is electrically connected to a third signal line, and
• wherein the other of the source and the drain of the fourth transistor is electrically connected to a fourth signal line,
• wherein each of the first, second, third and fourth transistors comprises an oxide semiconductor layer having a channel formation region, the oxide semiconductor layer comprising an In—Sn—Zn—O based semiconductor.