Method and system for open loop compensation of delay variations in a delay line

A delay compensation circuit for open loop compensation of delay variations in a delay line, comprising:

• a. a sensing circuit for sensing the Process, Voltage, Temperature (PVT) variations in the delay line;
• b. a first stage circuit connected to the sensing circuit, the first stage circuit comprising:
• i. a first sensitive transistor for generating a first sensitive current based on the PVT variations, the first sensitive current being a mirrored current from the sensing circuit;
• ii. a constant current source for generating a reference current, the reference current being independent of the PVT variations;
• iii. a first compensating transistor for generating a first compensation current based on the first sensitive current and the reference current;
• and
• iv. a first current mirror for mirroring the first compensation current as a second summing current;
• and
• v. a second stage circuit cascaded to the first stage circuit and connected to the sensing circuit, the second stage circuit comprising:
• vi. a second sensitive transistor for generating a second sensitive current based on the PVT variations, the second sensitive current being a mirrored current from the sensing circuit;
• and
• vii. a second compensating transistor for generating a second compensation current based on the second sensitive current and the second summing current, the second compensation current compensating the delay variations and having a sensitivity based on the sensitivities of the first and second sensitive currents.