# US 2011/0095358 A1 · Double-sided semiconductor structure and method for manufacturing same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2011/0095358 A1 - Document ID: US20110095358A1 - Status: Published application - Kind: A1 - Application number: 12/913,316 - Filed: 2010-10-27 - Published: 2011-04-28 - Earliest claimed: 2009-10-28 - Assignees: STMicrolectronics S.A. - Inventors: Monica Micciche'; Antonio Giuseppe Grimaldi; Gaetano Bazzano; Nicolò Frazzetto - Web page: https://patentgrep.com/patent/US20110095358A1 ## CPC - H10D 88/101: {comprising components on opposite major surfaces of semiconductor substrates} - H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs} - H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes} - H10D 30/663: {having both source contacts and drain contacts on the same surface, i.e. up-drain VDMOS} - H10D 30/665: {having edge termination structures} - H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors} - H10D 84/141: {VDMOS having built-in components} - H10D 84/146: {the built-in components being Schottky barrier diodes} - H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor structure including a substrate of semiconductor material of a first type of conductivity; a first semiconductor layer set in direct electrical contact with the substrate on a first side of the substrate; a second semiconductor layer set in direct electrical contact with the substrate on a second side of the substrate; a first active electronic device formed in the first semiconductor layer; and a second active electronic device formed in the second semiconductor layer. ## Claims ### Claim 1 A semiconductor structure comprising: a substrate of semiconductor material of a first type of conductivity; a first semiconductor layer arranged in direct electrical contact with the substrate on a first side of the substrate; a second semiconductor layer arranged in direct electrical contact with the substrate on a second side of the substrate; a first active electronic device formed in the first semiconductor layer; and a second active electronic device formed in the second semiconductor layer. ### Claim 2 (depends on 1) The structure according to claim 1, wherein the first active electronic device comprises at least a first conduction terminal, and the second active electronic device comprises at least a second conduction terminal, said semiconductor structure moreover comprising a third conduction terminal common to the first active electronic device and to the second active electronic device. ### Claim 3 (depends on 2) The structure according to claim 2, wherein the third conduction terminal extends through the second semiconductor layer as far as the substrate. ### Claim 4 (depends on 1) The structure according to claim 1, further comprising a first annular guard region, of a second type of conductivity, extending within the first semiconductor layer and facing a surface of the first semiconductor layer, and a second annular guard region, of the second type of conductivity, extending within the second semiconductor layer and facing a surface of the second semiconductor layer, said first annular guard region delimiting externally the first active electronic device, and said second annular guard region delimiting externally the second active electronic device. ### Claim 5 (depends on 1) The structure according to claim 1 wherein at least one between the first and second active electronic devices further comprises a first control terminal. ### Claim 6 (depends on 5) The structure according to claim 5, further comprising at least a second control terminal, wherein the first conduction terminal and the first control terminal are, respectively, a source terminal and a gate terminal of a first vertical-channel transistor device, and the second conduction terminal and the second control terminal are, respectively, a source terminal and a gate terminal of a second vertical-channel transistor device, and the third conduction terminal is a drain terminal common to the first and the second vertical-channel transistor devices. ### Claim 7 (depends on 6) The structure according to claim 6, wherein the first and the second active electronic devices comprise a respective plurality of source terminals and gate terminals of respective vertical-channel transistor devices. ### Claim 8 (depends on 5) The structure according to claim 5, wherein the first conduction terminal and the first control terminal are, respectively, a source terminal and a gate terminal of a first vertical-channel transistor device, the second conduction terminal is an anode terminal of a diode device, and the third conduction terminal forms both a drain terminal of the first vertical-channel transistor device and a cathode terminal of the diode device. ### Claim 9 (depends on 4) The structure according to claim 4, further comprising a conductive anode biasing region in electrical contact with the second annular guard region and with a portion of the second semiconductor layer delimited by the second annular guard region. ### Claim 10 (depends on 1) The structure according to claim 1, further comprising a third semiconductor layer, of a second type of conductivity, sandwiched between the substrate and the first semiconductor layer, and a fourth semiconductor layer, of the second type of conductivity, sandwiched between the substrate and the second semiconductor layer. ### Claim 11 (depends on 10) The structure according to claim 10, wherein the third conduction terminal extends through the second semiconductor layer and the fourth semiconductor layer as far as the substrate. ### Claim 12 A method for manufacturing a semiconductor structure comprising the steps of: providing a substrate of semiconductor material of a first type of conductivity and having a first side and a second side, opposite to one another; forming, on the first side of the substrate, a first semiconductor layer; forming, on the second side of the substrate, a second semiconductor layer; forming, in the first semiconductor layer, a first active electronic device; and forming, in the second semiconductor layer, a second active electronic device. ### Claim 13 (depends on 12) The method according to claim 12, wherein the step of forming the first semiconductor layer comprises epitaxially growing a semiconductor layer on the first side of the substrate, and the step of forming the second semiconductor layer comprises epitaxially growing a semiconductor layer on the second side of the substrate. ### Claim 14 (depends on 12) The method according to claim 12, further comprising the steps of forming, in the first semiconductor layer externally to the first active electronic device, a first annular guard region; and forming, in the second semiconductor layer externally to the second active electronic device, a second annular guard region. ### Claim 15 (depends on 12) The method according to claim 12 wherein the step of forming the first active electronic device comprises the steps of forming at least a first conduction terminal, and the step of forming the second active electronic device comprises forming at least a second conduction terminal, the method moreover comprising the step of forming, in the second semiconductor layer and, at least partially, in the substrate a third conduction terminal. ### Claim 16 (depends on 15) The method according to claim 15, wherein the step of forming the first active electronic device further comprises forming at least a first control terminal (17) and/or the step of forming the second active electronic device (12; 305) moreover comprises forming at least a second control terminal (27). ### Claim 17 (depends on 15) The method according to claim 15, wherein the step of forming the third conduction terminal comprises introducing dopant species of the first type of conductivity in the second semiconductor layer until the substrate) is reached. ### Claim 18 (depends on 15) The method according to claim 15, wherein the step of forming the third conduction terminal comprises etching the second semiconductor layer and, at least partially, the substrate to form a trench and filling said trench with conductive material of the first type of conductivity. ### Claim 19 (depends on 14) The method according to claim 14, further comprising the step of forming a conductive anode biasing region, on top of, and in direct electrical contact with, the second annular guard region and an anode region of the second semiconductor layer, said anode region being delimited by the second annular guard region. ### Claim 20 (depends on 12) The method according to claim 12, further comprising the steps of forming a third semiconductor layer, of a second type of conductivity, between the substrate and the first semiconductor layer, and forming a fourth semiconductor layer, of the second type of conductivity, between the substrate and the second semiconductor layer. ### Claim 21 (depends on 20) The method according to claim 20, wherein the steps of forming the third semiconductor layer and the fourth semiconductor layer comprise carrying out an epitaxial growth on the first and second sides of the substrate prior to formation of the first semiconductor layer and, respectively, the second semiconductor layer. ### Claim 22 (depends on 20) The method according to claim 20, wherein the steps of forming the third semiconductor layer and the fourth semiconductor layer comprise the steps of forming the first and second semiconductor layers and the steps of introducing dopant species of a second type of conductivity in a first region of interface between the first semiconductor layer and the substrate and in a second region of interface between the second semiconductor layer and the substrate.