Reliable communications in on-chip networks
AssigneeEmpire Technology Development LLC
InventorsWilliam H. Mangione-Smith, Onur Mutlu
Life of this patent
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Abstract
Techniques for reliable communication in an on-chip network of a multi-core processor are provided. Packets are tagged with tags that define reliability requirements for the packets. The packets are routed in accordance with the reliability requirements. The reliability requirements and routing using them can ensure reliable communication in the on-chip network.
Claims25
In a chip having an on-chip network providing communication among a plurality of cores, a method for delivering a packet in the on-chip network, the method comprising:
- originating the packet at an originating core included in the plurality of cores in the on-chip network, the core including a processor and a switch;
- tagging the packet with a tag that defines a reliability requirement for the packet, wherein the reliability requirement controls delivery of the packet in the on-chip network;
- and
- delivering the packet to a destination core in compliance with the reliability requirement, wherein the reliability requirement enables the on-chip network to dynamically adjust performance of the on-chip network in the delivery of the packet.
The method of claim 6, further comprising resending the packet by at least one of a network switch, a core, or a plurality of network switches and cores in cooperation.
A method for routing a packet in an on-chip network, the method comprising:
- receiving a packet at a core of a multi-core processor from an originating core, the core including at least a processor and a switch for routing packets;
- examining a reliability requirement associated with the packet, wherein the reliability requirement identifies delivery options for the packet in the on-chip network;
- and
- transmitting the packet in the on-chip network to a destination core while complying with the reliability requirement associated with the packet.
A processing device having an on-chip network for routing a packet, the processor comprising:
- a plurality of connections;
- a plurality of cores connected by the plurality of connections to form the on-chip network, each core including an originating core and a destination core, each core including a processor and a network switch, wherein the originating core generates the packet and tags the packet with a tag that defines a reliability requirement, wherein the packet is delivered to the destination core according to the reliability requirement.
Dependencies are inferred from the claim text.