US 2011/0087861 A1Published application

System for High-Efficiency Post-Silicon Verification of a Processor

AssigneeThe Regents of the University of Michigan

InventorsValeria Bertacco, Ilya Wagner

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Abstract

A post-silicon validation technique is able to craft randomized executable code, with known final outcomes, as a verification test that is executable on a hardware, such as a prototype microprocessor. A verification device is able to generate the test, in the form of programs, in such a way that at the end of the execution, the initial state of the test hardware is restored. Therefore, the final state of such a reversible program is known a priori. The technique may use a program generation algorithm, agnostic to any particular instruction set on the test hardware. In some examples, that algorithm is executed on the test hardware to generate the verification test, which is then executed on that test hardware. In other examples, the verification test is generated on another processor coupled to the test hardware. In either case, the verification test may contain initial and inverse operations determined from the test hardware.

Claims17

Dependent claims

A method of developing an executable verification test for examining a test processor capable of executing stored instructions, the method comprising:

a verification processor device identifying one or more initial operations from one or more instructions of the instruction set architecture (ISA) of the test processor;
the verification processor device determining one or more inverse operations, each corresponding to one of the initial operations;
and
the verification processor device generating the verification test comprising one or more stacks, wherein each stack is assigned to alter a register on the test processor, and each stack is assigned to a different pair of initial operations and inverse operations, wherein if there are a plurality of stacks the stacks are interleaved with each other, further whereby each stacks applies its initial operation to its register and then applies its inverse operation in the reverse order to its register, wherein the application of the inverse operation returns the register to a state before application of the initial operation of the stack.

1 more element

Dependencies are inferred from the claim text.