System cycle loading and storing of misaligned vector elements in a simd processor

An execution unit for transfer of a vector between a data memory and a vector register file in a single clock cycle and processing said vector, the execution unit comprising:

• said vector register file including a plurality of vector registers with at least one data port;
• each of said plurality of vector registers storing n vector elements, n being an integer no less than 2;
• said data memory comprised of at least n memory banks, each of said at least n memory banks having independent addressing and at least one data port, whereby said at least n memory banks are independently accessible in parallel and at the same time;
• address generation means coupled to said at least n memory banks for accessing n consecutive elements of said vector in said data memory in accordance with an address pointing to first vector element of said vector;
• and
• mapping means that is operably coupled between data ports of said at least n memory banks and said at least one data port of said vector register file for reordering vector elements during transfers of said vector between said vector register file and said data memory in accordance with said address.

A method for loading a plurality of vector elements of a source vector from a data memory to a vector register file in a single step, the method comprising:

• providing said data memory that is partitioned into a plurality of memory banks, each of said plurality of memory banks is independently addressable and at the same time, number of said plurality of memory banks is at least the same as the number of vector elements of said source vector;
• providing said vector register file with the ability to store a plurality of vectors;
• partitioning an input address pointing to first vector element of said source vector into two parts consisting of a bit-field of low-order address bits and a current line address consisting of remaining bit-field of high-order address bits, said bit-field of low-order address bits consists of K bits where 2K addresses span width of said data memory;
• calculating a next line address by adding value of one to said current line address;
• selecting an address for each of said plurality of memory banks as one of said current line address or said next line address in accordance with position of respective memory bank and said bit-field of low-order address bits so that consecutive vector elements of said source vector are accessed;
• addressing said plurality of memory banks with said selected respective addresses;
• reordering data output of said plurality of memory banks in accordance with said bit-field of low-order address bits;
• and
• storing said reordered data output into a selected vector of said vector register file.

An execution unit for transferring a misaligned vector between a data memory and a vector register file in a single clock cycle and processing said misaligned vector, the execution unit comprising:

• said data memory partitioned into even and odd memory banks with independent addressing containing respectively even and odd lines of data of said data memory, said data memory providing access to two consecutive lines in parallel;
• means for address generation for said even and odd memory banks for accessing all consecutive vector elements of said misaligned vector;
• a data selection circuit to select between vector element positions of data ports of said even and odd memory banks for accessing all consecutive elements of said misaligned vector;
• and
• a crossbar circuit for reordering vector elements during transfers between said vector register file and said data memory.