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AssigneeSTMicroelectronics (Rousset) SAS
InventorFrancois Tailliet
Estimating the term…
The memory device comprises a physical memory plane (PMP) comprising m first physical lines (RGP1i) extending along a first direction and n second physical lines (RGP2j) extending along a second direction, reception means for receiving a logical address (ADR) designating a first logical line (RG1i) and a second logical line (RG2j) of a matrix logical memory plane (PML), possessing 2p first logical lines extending along the first direction and 2q second logical lines extending along the second direction, in that m and n are each different from a power of two, m being a multiple of 2k, k being less than or equal to p, and the product of m and n being equal to the nearest integer above 2p+q, and in that it comprises means for addressing the physical memory plane (PMP) that are configured to address a first physical line and a part only of a second physical line on the basis of the content of the said logical address received and of the remainder of a Euclidean division of a part of the content of this logical address received by m/2k.
A memory device, comprising:
A memory device comprising:
A method of addressing a memory device, comprising a physical memory plane corresponding to a matrix logical memory plane, possessing 2p first logical lines extending along a first direction and 2q second logical lines extending along a second direction, the physical memory plane comprising m first physical lines extending along the first direction and n second physical lines extending along the second direction, m and n each being different from a power of two, m being a multiple of 2k, k being less than or equal to p, and the product of m and n being equal to the nearest integer above 2p+q, the method comprising:
Dependencies are inferred from the claim text.