Accessing a Multi-Channel Memory System Having Non-Uniform Page Sizes
AssigneeQUALCOMM Incorporated
InventorsFeng Wang, Matthew Michael Nowak, Jonghae Kim
Life of this patent
Estimating the term…
Abstract
A method includes predicting a memory access pattern of each master of a plurality of masters. The plurality of masters can access a multi-channel memory via a crossbar interconnect, where the multi-channel memory has a plurality of banks The method includes identifying a page size associated with each bank of the plurality of banks The method also includes assigning at least one bank of the plurality of banks to each master of the plurality of masters based on the memory access pattern of each master.
Claims43
An apparatus, comprising:
- a crossbar interconnect configured to:
- predict a memory requirement of a master having access to a multi-channel memory;
- identify a page size associated with each channel of the multi-channel memory;
- and
- assign a first particular channel of the multi-channel memory to the master based on the predicted memory requirement of the master and based on the page size associated with the first particular channel.
An apparatus comprising:
- means for predicting a page size requirement of a master having access to a multi-channel memory;
- means for identifying a page size associated with each channel of the multi-channel memory;
- and
- means for assigning a channel of the multi-channel memory to the master based on the page size requirement of the master and based on the page size associated with the channel.
A method, comprising:
- predicting a memory access pattern of each master of a plurality of masters, the plurality of masters having access to a multi-channel memory via a crossbar interconnect, wherein the multi-channel memory has a plurality of banks;
- identifying a page size associated with each bank of the plurality of banks;
- and
- assigning at least one bank of the plurality of banks to each master of the plurality of masters based on the memory access pattern of each master.
A method comprising:
- a first step for predicting a memory requirement of a master having access to a multi-channel memory;
- a second step for identifying a page size associated with each channel of the multi-channel memory;
- and
- a third step for assigning a channel of the multi-channel memory to the master based on the memory requirement of the master and based on the page size associated with the channel.
A computer readable tangible medium storing instructions executable by a computer, the instructions comprising:
- instructions that are executable by the computer to predict a memory requirement of a master having access to a multi-channel memory;
- instructions that are executable by the computer to identify a page size associated with each channel of the multi-channel memory;
- and
- instructions that are executable by the computer to assign a channel of the multi-channel memory to the master based on the memory requirement of the master and based on the page size associated with the channel.
A method comprising:
- receiving design information representing at least one physical property of a semiconductor device, the semiconductor device comprising:
- a multi-channel memory, each channel connected to at least one memory bank;
- and
- a crossbar interconnect configured to:
- predict a memory requirement of a master having access to the multi-channel memory;
- identify a page size associated with each channel of the multi-channel memory;
- and
- assign a channel of the multi-channel memory to the master based on the predicted memory requirement of the master and based on the page size associated with the channel;
- transforming the design information to comply with a file format;
- and
- generating a data file including the transformed design information.
A method comprising:
- receiving a data file including design information corresponding to a semiconductor device and fabricating the semiconductor device according to the design information, wherein the semiconductor device comprises:
- a multi-channel memory, each channel connected to at least one memory bank;
- and
- a crossbar interconnect configured to:
- predict a memory requirement of a master having access to the multi-channel memory;
- identify a page size associated with each channel of the multi-channel memory;
- and
- assign a channel of the multi-channel memory to the master based on the predicted memory requirement of the master and based on the page size associated with the channel.
A method comprising:
- receiving design information including physical positioning information of a packaged semiconductor device on a circuit board, the packaged semiconductor device including a semiconductor structure comprising:
- a multi-channel memory, each channel connected to at least one memory bank;
- and
- a crossbar interconnect configured to:
- predict a memory requirement of a master having access to the multi-channel memory;
- identify a page size associated with each channel of the multi-channel memory;
- and
- assign a channel of the multi-channel memory to the master based on the predicted memory requirement of the master and based on the page size associated with the channel.
A method comprising:
- receiving a data file including design information including physical positioning information of a packaged semiconductor device on a circuit board;
- and
- manufacturing the circuit board configured to receive the packaged semiconductor device according to the design information, wherein the packaged semiconductor device comprises:
- a multi-channel memory, each channel connected to at least one memory bank;
- and
- a crossbar interconnect configured to:
- predict a memory requirement of a master having access to the multi-channel memory;
- identify a page size associated with each channel of the multi-channel memory;
- and
- assign a channel of the multi-channel memory to the master based on the predicted memory requirement of the master and based on the page size associated with the channel.
Dependencies are inferred from the claim text.