Monitoring cache usage in a distributed shared cache
AssigneeIntel Corporation
InventorsLi Zhao, Ravishankar Iyer, Rameshkumar G. Illikkal, Erik G. Hallnor, Martin G. Dixon, Donald K. Newell
Life of this patent
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AssigneeIntel Corporation
InventorsLi Zhao, Ravishankar Iyer, Rameshkumar G. Illikkal, Erik G. Hallnor, Martin G. Dixon, Donald K. Newell
Estimating the term…
An apparatus, method, and system are disclosed. In one embodiment the apparatus includes a cache memory, which a number of sets. Each of the sets in the cache memory have several cache lines. The apparatus also includes at least one process resource table. The process resource table maintains a cache line occupancy count of a number of cache lines. Specifically, the cache line occupancy count for each cache line describes the number of cache lines in the cache storing information utilized by a process running on a computer system. Additionally, the process resource table stores the occupancy count of less cache lines than the total number of cache lines in the cache memory.
An apparatus, comprising:
A method, comprising:
A system, comprising:
The system of claim 20, wherein the multi-core processor is further operable to:
The system of claim 20, further comprising:
Dependencies are inferred from the claim text.