Processor and control method

A control method of a processor including a first processing unit that has a first memory unit and performs processing, a second processing unit that performs processing, a second memory unit that includes all of the data held by the first memory unit and that holds status information specifying a status of data held in the first memory unit, the control method comprising:

• receiving a first access request for data of a first address from the second processing unit;
• outputting a request for reading out data of a first address to the first processing unit when first status information of the data of the first address indicates that the data of the first address is held in the first memory unit in an exclusive state or owned state;
• and
• allowing the second processing unit to access data of the first address included at the second memory unit upon receiving a no-data-modification notification indicating the data of the first address is not modified by the first processing unit.