Semiconductor memory device and data processing system
AssigneeElpida Memory, Inc.
InventorsHomare Sato, Junichi Hayashi
Life of this patent
Estimating the term…
Abstract
To include a plurality of core chips to which different pieces of chip information from each other are given in advance. A first refresh command is divided into a plurality of second refresh commands having different timings from each other, and a refresh operation is performed on a core chip for which a count value of the second refresh commands and at least a portion of the chip information match each other. With this configuration, even when the second refresh command is commonly supplied to a plurality of core chips, it is possible to shift a timing for the refresh operation in each of the core chips. Therefore, it is possible to reduce a peak current at the time of the refresh operation.
Claims15
A semiconductor device comprising:
- a plurality of core chips assigned different chip identification information from each other;
- a refresh control circuit that receives a first refresh command and generates a plurality of second refresh commands having different phases from each other in response to the first refresh command;
- and
- a first counter circuit that counts the second refresh commands and generates a count value, wherein
- each of the core chips performs a refresh operation when the count value matches at least a portion of the chip identification information assigned thereto.
A semiconductor device comprising:
- a plurality of core chips each including a plurality of memory cells that requires a refresh operation to maintain data stored therein, where chip identification information is assigned to each of the core chips;
- and
- an interface chip that commonly supplies a refresh command to the core chips, wherein
- each of the core chips includes a first counter circuit that counts the refresh command and a comparing circuit that determines whether to perform the refresh operation based on a count value of the first counter circuit and at least a portion of the chip identification information assigned to the core chip.
A semiconductor device mounted on a substrate, comprising:
- an interface chip mounted on the substrate, receiving a refresh command from the substrate, outputting a plurality of first internal refresh signals in sequence in response to the refresh command;
- a first core chip mounted on the interface chip, holding first chip identification information, counting the number of the first internal refresh signals, comparing the first chip identification information with the number of the first internal refresh signals, and generating a second internal refresh signal to perform a refresh operation in the first core chip when the first chip identification information is coincident with the number of the first internal refresh signals;
- and
- a second core chip mounted on the first core chip, holding second chip identification information which is different from the first chip identification information, counting the number of the first internal refresh signals, comparing the second chip identification information with the number of the first internal refresh signals, and generating a third internal refresh signal to perform a refresh operation in the second core chip when the second chip identification information is coincident with the number of the first internal refresh signals.
Dependencies are inferred from the claim text.