Interrupt Masking for Multi-Core Processors
AssigneeEmpire Technology Development LLC
InventorEzekiel John Joseph Kruglick
Life of this patent
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Abstract
Technologies are generally described herein for handling interrupts within a multi-core processor. A core specific interrupt mask (“CIM”) can be adapted to influence the assignment of interrupts to particular processor cores in the multi-core processor. Available processor cores can be identified by evaluating the CIM. An interrupt with an interrupt service routine (“ISR”) that is received by the multi-core processor can be assigned to one or more of the available processor cores identified by the CIM.
Claims22
A method for handling interrupts within a multi-core processor having a plurality of processor cores, the method comprising:
- receiving an interrupt associated with an interrupt service routine;
- evaluating a core interrupt mask to identify one or more available processor cores from the plurality of processor cores;
- and
- assigning the interrupt service routine associated with the received interrupt to at least one of the one or more available processor cores.
A system for handling interrupts within a multi-core processor including a plurality of processor cores, the system comprising:
- an interrupt line adapted to communicate an interrupt request to the multi-core processor;
- a core interrupt mask adapted to specify a status associated with each of the plurality of processor cores, wherein the status corresponds to either an available processor core or an unavailable processor core;
- and
- an interrupt controller configured to
- receive an interrupt request via the interrupt line,
- evaluate the core interrupt mask to identify one or more available processor cores, and
- assign handling of the interrupt request to one of the available processor cores.
A computer storage medium having computer-executable instructions stored thereon which, when executed by a computer system that includes a multi-core processor with a plurality of processor cores, cause the computer system to:
- configure a core interrupt mask to specify a status associated with each of the plurality of processor cores, wherein the status corresponds to either an available processor core or an unavailable processor core;
- receive an interrupt request associated with an interrupt service routine;
- evaluate the core interrupt mask to identify one or more available processors;
- and
- assign the interrupt service routine away associated with the received interrupt request to at least one of the available processor cores.
Dependencies are inferred from the claim text.