Enhanced I/O Performance in a Multi-Processor System Via Interrupt Affinity Schemes
AssigneeEmulex Design & Manufacturing Corporation
InventorsQiang LIU, Allen Russell Andrews, David Bradley Baldwin
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Abstract
Disclosed herein is a method for improving Input/Output (I/O) performance in a host system having multiple CPUs. Under this method, various interrupt affinity schemes are provided, which associate multiple processors, interrupts, and I/O channels for sending the interrupts, thereby allowing the interrupts to be almost evenly loaded among the multiple I/O channels and processors. Also, data locality (“warm cache”) can be achieved through the interrupt affinity schemes that associate each interrupt to its source processor, namely, the processor originating the I/O request that results in the interrupt.
Claims51
A method of improving Input/Output (I/O) performance in a multi-processor system, said method comprising:
- creating an interrupt affinity scheme having associations between a plurality of processors, interrupt identifiers and I/O channels;
- generating an interrupt upon completion of an I/O command;
- and
- sending said interrupt from a particular I/O channel of said I/O channels to a particular processor of said processors in accordance with said interrupt affinity scheme, said interrupt having an interrupt identifier associated with said particular processor and said particular I/O channel.
A method of improving CPU usage in handling Input/Output (I/O) performance, said method comprising:
- identifying an interrupt affinity scheme in a system having a number of processors, said interrupt affinity scheme comprising associations between said processors and a number of interrupt identifiers to be requested for generating interrupts upon I/O completions;
- and
- associating said interrupt identifiers with a number of I/O channels in accordance with said interrupt affinity scheme such that interrupts sent from said I/O channels are evenly distributed to each of said processors for processing.
A method of improving CPU usage in handling Input/Output (I/O) performances in a multi-processor system, said method comprising:
- detecting a total number of interrupt identifiers available in said system, each interrupt identifier to be used for generating an interrupt upon an I/O completion;
- for each interrupt identifier, creating a worker kernel thread for handling interrupts having the interrupt identifier;
- and
- binding each created worker kernel thread to a unique processor among multiple processors in said system, said unique processor associated with the interrupt identifier corresponding to the worker kernel thread according to an interrupt mapping scheme comprising associations between different processors and said interrupt identifiers.
A method for processing interrupts in a multi-processor system, said method comprising:
- receiving an interrupt triggered by completion of an Input/Output (I/O) command, said interrupt having an interrupt identifier;
- identifying a processor from multiple processors for processing said interrupt, said processor associated with said interrupt identifier according to an interrupt affinity scheme comprising associations between said multiple processors and a number of interrupt identifiers including said interrupt identifier;
- and
- processing said interrupt at said processor.
A multi-processor system comprising:
- a host comprising multiple processors, each of said processors configured to generate Input/Output (I/O) requests and process interrupts;
- and
- a host bus adapter coupled with said host, said host bus adapter comprising having multiple I/O channels, each of said I/O channels configured to receive said I/O requests from said host,
- wherein said host bus adapter is configured to generate said interrupts upon completion of said I/O requests and select one of said multiple I/O channels for sending each of said interrupts back to said host in accordance with an interrupt affinity scheme comprising associations between said processors, multiple interrupt identifiers and said I/O channels.
A computer readable storage medium comprising computer-executable instructions, said instructions, when executed, causing a computer to:
- create an interrupt affinity scheme comprising associations between a plurality of processors, interrupt identifiers and I/O channels in a multi-processor system;
- generate an interrupt upon completion of an I/O command;
- and
- send said interrupt from a particular I/O channel of said I/O channels to a particular processor of said processors in accordance with said interrupt affinity scheme, said interrupt having an interrupt identifier associated with said particular processor and said particular I/O channel.
A computer readable storage medium comprising computer-executable instructions, said instructions, when executed, causing a computer to:
- detect a total number of interrupt identifiers available in said system, each interrupt identifier to be used for generating an interrupt upon an I/O completion;
- for each interrupt identifier, create a worker kernel thread for handling interrupts having the interrupt identifier;
- and
- bind each created worker kernel thread to a unique processor among multiple processors in said system, said unique processor associated with the interrupt identifier corresponding to the worker kernel thread according to an interrupt mapping scheme comprising associations between different processors and said interrupt identifiers.
A computer readable storage medium comprising computer-executable instructions, said instructions, when executed, causing a computer to:
- receive an interrupt triggered by completion of an Input/Output (I/O) command, said interrupt having an interrupt identifier;
- identify a processor from multiple processors for processing said interrupt, said processor associated with said interrupt identifier according to an interrupt affinity scheme comprising associations between said multiple processors and a number of interrupt identifiers including said interrupt identifier;
- and
- process said interrupt at said processor.
Dependencies are inferred from the claim text.