Semiconductor device, control method for the semiconductor device and information processing system including the same
AssigneeElpida Memory, Inc.
InventorsChikara Kondo, Naohisa Nishioka
Life of this patent
Estimating the term…
Abstract
The core chips each include a timing control circuit that outputs a timing signal synchronized with the outputting of parallel data to the interface chip. The interface chip includes a data input circuit that captures parallel data in synchronization with the timing signal. With this arrangement, the timing to output the parallel data and the timing to capture the parallel data are both synchronized with the timing signal generated in the core chips. Therefore, even if there is a difference in operation speed between each core chip and the interface chip, the parallel data can be accurately captured on the interface chip side.
Claims24
A semiconductor device comprising:
- at least one core chip that outputs parallel data comprising a plurality of parallel bits;
- and
- an interface chip that converts the parallel data supplied from the core chip into serial data comprising a plurality of series bits, and outputs the serial data to outside, wherein
- the core chip includes a timing control circuit that outputs a timing signal synchronized with an output of the parallel data to the interface chip, and
- the interface chip includes a data input circuit that captures the parallel data in synchronization with the timing signal transferred from the core chip.
A method for controlling a semiconductor device comprising:
- providing the semiconductor device that includes:
- at least one core chip that outputs parallel data comprising a plurality of parallel bits;
- and an interface chip that converts the parallel data supplied from the core chip into serial data comprising a plurality of series bits, and outputs the serial data to outside;
- generating a timing signal in the core chip;
- supplying the timing signal from the core chip to the interface chip;
- outputting the parallel data from the core chip to the interface chip in synchronization with the timing signal;
- and
- capturing the parallel data in the interface chip in synchronization with the timing signal supplied from the core chip.
A data processing system comprising:
- a semiconductor device;
- and
- a controller that is connected to the semiconductor device, wherein
- the semiconductor device comprising:
- a plurality of core chip that output parallel data comprising a plurality of parallel bits;
- and
- an interface chip that converts the parallel data supplied from the core chips into serial data comprising a plurality of series bits, and outputs the serial data to the controller, wherein
- each of the core chips includes a timing control circuit that outputs a timing signal synchronized with an output of the parallel data to the interface chip, and
- the interface chip includes a data input circuit that captures the parallel data in synchronization with the timing signal transferred from the core chips, and wherein
- the controller issues an external read command to the interface chip,
- the interface chip issues an internal read command to the core chips, upon receipt of the external read command from the controller, and
- one of the core chips outputs the parallel data in response to the internal read command to the interface chip.
Dependencies are inferred from the claim text.