Direct access memory controller with multiple sources, corresponding method and computer program
AssigneeCommissar. A L'energ. Atom. Et Aux Energ. Altern.
InventorsYves DURAND, Christian Bernard
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AssigneeCommissar. A L'energ. Atom. Et Aux Energ. Altern.
InventorsYves DURAND, Christian Bernard
Estimating the term…
This direct access memory controller (10, 20) is programmed to transfer data from several data sources (121, . . . , 12i, . . . , 12n) to at least one addressee (14) for these data, through several buffer memories (161, . . . , 16i, . . . , 16n). It comprises a read management module (30) designed to read data stored in the buffer memories (161, . . . , 16i, . . . , 16n) and to transfer them in sequence to the addressee (14) and read pointers (PL1, PL2) storage means (38) associated respectively with each buffer memory respectively. For each buffer memory (161, . . . , 16i, . . . , 16n), the controller (10, 20) comprises means of executing a firmware (401, . . . , 40i, . . . , 40n) to read data and update the read pointer associated with this buffer memory, and it comprises means (30, 401, . . . , 40i, . . . , 40n) of synchronising execution of the firmwares as a function of a predetermined order of data originating from buffer memories required in the data sequence to be transferred to the addressee.
Direct memory access controller (10, 20) for transferring data from several data sources (121, . . . , 12i, . . . , 12n) to at least one addressee (14) for these data, through several buffer memories (161, . . . , 16i, . . . , 16n) each comprising a predetermined number of successive elementary memory locations, the access controller comprising a read management module (30) designed to read data stored in the buffer memories (161, . . . , 16i, . . . , 16n) and to transfer them in sequence to the addressee (14) and read pointers (PL1, PL2) storage means (38) associated respectively with each buffer memory, each read pointer indicating an elementary location of the buffer memory with which it is associated and in which data can be read, characterised in that the buffer memories (161, 16i, . . . , 16n) are associated respectively with each data source (121, . . . , 12i, . . . , 12n) and for each buffer memory the controller (10, 20) comprises means of executing a firmware (401, . . . , 40i, . . . , 40n) to read data and update the read pointer associated with this buffer memory, and in that it comprises means (30, 401, . . . , 40i, . . . , 40n) of synchronising execution of the firmwares as a function of a predetermined order of data originating from buffer memories required in the data sequence to be transferred to the addressee.
Dependencies are inferred from the claim text.