Systems and Methods of Efficient Library Characterization for Integrated Circuit Cell Libraries

An apparatus for performing an efficient library characterization process on a circuit of a logic gate having a plurality of transistors and a plurality of nodes defining interconnection points in the circuit, comprising:

• a module to read process models that describe process variations data, the process models being used to predict influence on a switching characteristics through circuit simulations and a Response Surface Method (RSM);
• a module to enable a user to input user commands;
• a module to determine a plurality of arcs, each of the plurality of arcs represents an input-to-output path pair in the logic gate, and determining a plurality of vectors for each of the plurality of arcs, each of the plurality of vectors represents a possible input data bits to inputs and the plurality of nodes;
• and
• a module to perform circuit pruning process, the circuit pruning process includes identifying active portions of the circuit, the active portions being portions of the circuit that affect circuit performance,
• wherein, the circuit simulation is run to predict process variation influence on a switching characteristic on a plurality of transistors in the pruned circuit.

A computer readable media having program instructions for efficient library characterization of a circuit of a logic gate having a plurality of transistors and a plurality of nodes defining interconnection points in the circuit, the computer readable media comprising:

• (a) program instructions for determining a plurality of vectors for a plurality of arcs, each of the plurality of vectors represents possible data bits to inputs and nodes of the logic gate;
• (b) program instructions for selecting a plurality of substantially distinct vectors from the plurality of vectors for each of the plurality of arcs;
• (c) program instructions for performing circuit pruning for each of the plurality of substantially distinct vectors taking each one substantially distinct vector at a time, the circuit pruning includes identifying an active circuit for each vector, the active circuit is identified by determining which circuit features are activated when applying a particular one of the substantially distinct vectors;
• (d) program instructions for performing circuit simulations limited to a plurality of transistors in the active circuit;
• (e) program instructions for repeating (c) and (d) for remaining ones of the plurality of substantially distinct vectors;
• and
• (f) program instructions for storing results of the circuit simulations on a non-volatile compute readable media, for each active circuit corresponding to each of the plurality of substantially distinct vectors.