Method for fabricating semiconductor device with buried gates
AssigneeHynix Semiconductor Inc.
InventorsJi-Min LIM, Kyung-Ho Hwang
Life of this patent
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Abstract
A method for fabricating a semiconductor device includes providing a substrate including cell regions and peripheral regions; selectively forming a gate conductive layer over the substrate in the peripheral regions, forming a sealing layer over the substrate with the gate conductive layer formed thereon, forming an insulation layer over the sealing layer to cover the substrate with the gate conductive layer formed on the substrate, planarizing the insulation layer to expose the sealing layer formed over the gate conductive layer, and forming a plurality of plugs in the cell regions, the plurality of the plugs penetrating the insulation layer and the sealing layer.
Claims23
A method for fabricating a semiconductor device, comprising:
- providing a substrate including cell regions and peripheral regions;
- selectively forming a gate conductive layer over the substrate in the peripheral regions;
- forming a sealing layer over the substrate with the gate conductive layer formed thereon;
- forming an insulation layer over the sealing layer to cover the substrate with the gate conductive layer formed on the substrate;
- planarizing the insulation layer to expose the sealing layer formed over the gate conductive layer;
- and
- forming a plurality of plugs in the cell regions, the plurality of the plugs penetrating the insulation layer and the sealing layer.
A method for fabricating a semiconductor device, comprising:
- providing a substrate including cell regions and peripheral regions;
- forming a gate conductive layer over the substrate;
- etching the gate conductive layer by using a cell open mask;
- forming a sealing layer over the substrate with the gate conductive layer formed thereon;
- forming an insulation layer over the sealing layer to cover the substrate with the gate conductive layer formed on the substrate;
- planarizing the insulation layer to expose the sealing layer formed over the gate conductive layer;
- forming a plurality of plugs in the cell regions, the plurality of the plugs penetrating the insulation layer and the sealing layer;
- selectively removing the sealing layer formed over the gate conductive layer;
- and
- forming peripheral gates by patterning the gate conductive layer.
Dependencies are inferred from the claim text.