Methods of Forming Integrated Circuit Chips Having Vertically Extended Through-Substrate Vias Therein

A method of forming a semiconductor device, the method comprising:

• forming an integrated circuit on a top surface of a semiconductor substrate;
• forming a dielectric layer covering the integrated circuit device on the top surface of the semiconductor substrate;
• forming a through-via electrode extending into the substrate through the dielectric layer;
• forming a multi-level metal pattern on the dielectric layer to electrically contact the through-via electrode;
• and
• reducing a thickness of a first portion of the semiconductor substrate disposed under and corresponding to the integrated circuit and reducing a thickness of a second portion of the semiconductor substrate disposed under and corresponding to the through-via electrode until the thickness of the second portion becomes substantially zero, wherein an amount of the reduced thickness of the first portion is substantially same as an amount of the reduced thickness of the second portion.

A method of forming a semiconductor device, the method comprising:

• forming an integrated circuit on a top surface of a semiconductor substrate;
• forming a dielectric layer covering the integrated circuit device on the top surface of the semiconductor substrate;
• forming a through-via electrode extending into the substrate through the dielectric layer;
• forming a multi-level metal pattern on the dielectric layer to electrically contact the through-via electrode;
• and
• grinding an entire bottom surface of the semiconductor substrate until the substrate disposed under and corresponding to a bottom surface of the through-via electrode is completely removed.

A method of forming a semiconductor device, the method comprising:

• forming an integrated circuit on a top surface of a semiconductor substrate;
• forming a dielectric layer covering the integrated circuit device on the top surface of the semiconductor substrate;
• forming a via hole extending into the substrate through the dielectric layer;
• forming a spacer insulating layer on side and bottom walls of the via hole;
• and then
• filling the via hole with an electrically conductive through-via electrode to form a through-via electrode extending into the substrate through the dielectric layer;
• forming a multi-level metal pattern on the dielectric layer to electrically contact the through-via electrode;
• and
• grinding an entire bottom surface of the semiconductor substrate until the spacer insulating layer disposed on a bottom surface of the through-via electrode is exposed.