Methods of Forming Field Effect Transistors on Substrates
AssigneeMicron Technology, Inc.
InventorsRobert J. Hanson, Sanh D. Tang
Life of this patent
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Abstract
The invention includes methods of forming field effect transistors. In one implementation, the invention encompasses a method of forming a field effect transistor on a substrate, where the field effect transistor comprises a pair of conductively doped source/drain regions, a channel region received intermediate the pair of source/drain regions, and a transistor gate received operably proximate the channel region. Such implementation includes conducting a dopant activation anneal of the pair of source/drain regions prior to depositing material from which a conductive portion of the transistor gate is made. Other aspects and implementations are contemplated.
Claims29
1-13. (canceled)
A method of forming a field effect transistor on a substrate, the field effect transistor comprising a pair of conductively doped source/drain regions, a channel region received intermediate the pair of source/drain regions, and a transistor gate received operably proximate the channel region, the method comprising:
- ion implanting conductivity enhancing impurity dopant into semiconductive material of the substrate to form highest dopant concentration portions of the pair of source/drain regions;
- conducting a dopant activation anneal of the highest dopant concentration portions of the pair of source/drain regions;
- and
- after the dopant activation anneal, depositing material from which a conductive portion of the transistor gate is made.
A method of forming a field effect transistor on a substrate, the field effect transistor comprising a pair of conductively doped source/drain regions, a channel region received intermediate the pair of source/drain regions, and a transistor gate received operably proximate the channel region, the method comprising:
- ion implanting conductivity enhancing impurity dopant into an implant region of semiconductive material of the substrate to a highest dopant concentration for the pair of source/drain regions;
- after the ion implanting, conducting a dopant activation anneal of the implant region;
- after the dopant activation anneal, etching an opening through the implant region into semiconductive material of the substrate;
- and
- forming gate dielectric and conductive material of the transistor gate within the opening.
31-37. (canceled)
A method of forming an n-channel field effect transistor and a p channel field effect transistor on a substrate, said transistors respectively comprising a pair of conductively doped source/drain regions, a channel region received intermediate the pair of source/drain regions, and a transistor gate received operably proximate the channel region, the method comprising:
- ion implanting p-type conductivity enhancing impurity dopant into semiconductive material of the substrate to form highest dopant concentration portions of the pair of source/drain regions of the p-channel field effect transistor;
- ion implanting n-type conductivity enhancing impurity dopant into semiconductive material of the substrate to form highest dopant concentration portions of the pair of source/drain regions of the n-channel field effect transistor;
- simultaneously conducting a dopant activation anneal of the highest dopant concentration portions of the pair of source/drain regions of each of the n-channel field effect transistor and of the p-channel field effect transistor;
- and
- after the dopant activation anneal, depositing material from which conductive portions of the transistor gates are made.
43-48. (canceled)
A method of forming an n-channel field effect transistor and a p channel field effect transistor on a substrate, said transistors respectively comprising a pair of conductively doped source/drain regions, a channel region received intermediate the pair of source/drain regions, and a transistor gate received operably proximate the channel region, the method comprising:
- ion implanting p-type conductivity enhancing impurity dopant into a first region of semiconductive material of the substrate to a highest dopant concentration for the pair of source/drain regions of the p-channel field effect transistor;
- ion implanting n-type conductivity enhancing impurity dopant into a second region of semiconductive material of the substrate to a highest dopant concentration for the pair of source/drain regions of the n-channel field effect transistor;
- simultaneously conducting a dopant activation anneal of the first and second regions;
- after the dopant activation anneal, etching a first opening through the first region into semiconductive material of the substrate and etching a second opening through the second region into semiconductive material of the substrate;
- forming gate dielectric within the first and second openings;
- and
- forming conductive material of the transistor gate of the p-channel field effect transistor over the gate dielectric within the first opening and conductive material of the transistor gate of the n-channel field effect transistor over the gate dielectric within the second opening.
50-52. (canceled)
Dependencies are inferred from the claim text.