Cmos image sensor with asymmetric well structure of source follower
AssigneeCrosstek Capital, LLC
InventorHee-Jeong Hong
Life of this patent
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Abstract
Provided is a CMOS image sensor with an asymmetric well structure of a source follower. The CMOS image sensor includes: a well disposed in an active region of a substrate; a drive transistor having one terminal connected to a power voltage and a first gate electrode disposed to cross the well; and a select transistor having a drain-source junction between another terminal of the drive transistor and an output node, and a second gate electrode disposed in parallel to the drive transistor. A drain region of the drive transistor and a source region of the select transistor are asymmetrically arranged.
Claims23
1-13. (canceled)
A method, comprising:
- disposing a well of a first conductivity type on a substrate of the first conductivity type;
- disposing a first impurity region of a drive transistor in the well;
- forming a first gate electrode of a second conductivity type for the drive transistor such that the first gate electrode is connected to the first impurity region;
- forming a second gate electrode of the second conductivity type for a select transistor such that the second gate electrode is formed in parallel to the first gate electrode;
- and
- disposing a second impurity region of the second conductivity type in the substrate such that the second impurity region is coupled to the second gate electrode and an output node of a unit pixel, wherein a width of the well disposed under the second impurity region is in a range from approximately −0.1 μm to approximately −0.33 μm.
A method, comprising:
- disposing a well in an active region of a substrate;
- forming a drive transistor including:
- a terminal coupled to a power voltage;
- and
- a first gate electrode formed across the well;
- and
- forming a select transistor including:
- a drain-source junction between another terminal of the drive transistor and an output node of a unit pixel;
- a second gate electrode formed in parallel to the first gate electrode;
- and
- an impurity region, wherein a width of the well disposed under the impurity region is in a range from approximately −0.1 μm to approximately −0.33 μm.
A method, comprising:
- disposing a well in an active region of a substrate;
- forming a drive transistor including:
- a drain region connected to a power voltage, and
- a first gate electrode formed on the well;
- and
- forming a select transistor including:
- a source region connected to an output node of a unit pixel;
- and
- a second gate electrode formed in parallel to the first gate electrode;
- wherein said forming a drive transistor and said forming a select transistor asymmetrically arrange the drain region of the drive transistor and the source region of the select transistor in the well;
- and
- wherein said forming a select transistor forms the second gate electrode such that an end of the well is disposed below and within a footprint of the second gate electrode.
A method, comprising:
- forming a photodiode in a substrate;
- forming in the substrate a floating diffusion node configured to receive charge from the photodiode;
- forming a drive transistor including a first gate electrode coupled to the floating diffusion node and formed across a well of the substrate;
- and
- forming a select transistor coupled between the drive transistor and an output node of a unit pixel and including a second gate electrode formed across the well;
- wherein said forming a select transistor comprises forming the second gate electrode such that an end of the well is disposed below and within a footprint of the second gate electrode.
A method, comprising:
- forming a photodiode in a substrate;
- disposing, in the substrate, a floating diffusion node configured to receive charge from the photodiode;
- forming a drive transistor including a first gate electrode that is coupled to the floating diffusion node and that is formed across a well of the substrate;
- and
- forming a select transistor coupled between the drive transistor and an output node of a unit pixel and including a second gate electrode formed across the well;
- wherein said forming a select transistor forms the second gate electrode such that at least a portion of the second gate electrode extends beyond an end of the well.
Dependencies are inferred from the claim text.