High utilization universal logic array with variable circuit topology and logistic map circuit to realize a variety of logic gates with constant power signatures

A logistic map circuit comprising:

• a first MOSFET device with a p-channel type configuration with a gate coupled to an input voltage (Vin1), a source coupled to a first current source (I11) to establish a first MOSFET source current;
• a second MOSFET device with an n-channel type configuration with a gate coupled to the voltage source (Vin1), a drain coupled to a second current source (I21) to establish a second MOSFET drain current;
• and
• a summing point for the first MOSFET source current and the second MOSFET drain current, the summing point formed as a current mirror with a common gate coupled to a drain of the first MOSFET device and a source of the second MOSFET device, where the current mirror produces a summed non-linear output current (Io) proportional to Io=K1(Vin1−VT)2 that corresponds to one of a plurality of different logic gates responsive to adjusting input voltage (Vin1), where K1 is a conductivity constant attribute and VT is a threshold voltage attribute of at least one of the first MOSFET device and the second MOSFET device, and the first MOSFET source current and the second MOSFET drain current limit a value of output current (Io).

A universal logic array with variable circuit topology comprising:

• a plurality of array elements where each array element includes a first set of MOSFET devices with a p-channel type configuration and a second set of MOSFET devices with an n-channel type configuration;
• and
• at least one of a metallization layer and a via connection to form an interconnection between one or more of the first set of MOSFET devices and the second set of MOSFET devices in at least one of the array elements to produce a circuit topology to implement at least one of a Boolean function and a chaotic function and a logic function,
• wherein the chaotic function produces a non-linear output current that corresponds to one of a plurality of different logic gates responsive to adjusting an input voltage to the array element.

A substantially constant current logic circuit comprising:

• a first logistic map that takes input logic levels and Boolean logic combinations to generate a Boolean logic ONE to keep a supply current substantially constant for a logical ONE transition;
• and
• a second logistic map that takes the input logic levels and the Boolean logic combinations to generate a Boolean logic ZERO to keep a supply current substantially constant for a logical ZERO transition,
• wherein a supply transition current for the logical ONE transition and the logical ZERO transition are substantially equal.

A substantially constant current logic network comprising:

• a collection of j logic circuits, where for each logic circuit r (r=1 to j) comprising:
• a first logistic map that takes an rth input voltage and Boolean logic combinations to generate a Boolean logic ONE to keep a supply current substantially constant for a logical ONE transition;
• and
• a second logistic map that takes the rth input voltage and Boolean logic combinations to generate a Boolean logic ZERO to keep a supply current substantially constant for a logical ZERO transition,
• wherein a supply transition current for the logical ONE transition and the logical ZERO transition are substantially equal;
• and
• wherein the supply transition current for any input logic levels is substantially equal.

A system for masking data comprising:

• an encryption mask module configured to receive an encryption mask with a chaotic function data to apply a mask on data to form chaotic masked data;
• an encryption module for encrypting the chaotic masked data to form encrypted chaotic masked data;
• and
• an encryption un-mask module configured to receive the encryption mask with the chaotic function data to apply a mask on masked encrypted data to form un-masked encrypted data.