Zero-latency network on chip (NoC)
AssigneeQUALCOMM Technologies, Inc.
InventorsJean-Jacques Lecler, Philippe Boucard
Life of this patent
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Abstract
Packet format configurability is extended for packets transported on physical links of an Intellectual Property (IP) core interconnect by using at least two independent parameters: one parameter governing data-width and one parameter governing latency penalty. The at least two independent parameters allow creation of transport protocol packets without additional latency insertion, which is useful for low-latency applications. The at least two independent parameters also allow creation of narrow packets with multi-cycle additional latency, which is useful for latency tolerant, area sensitive applications.
Claims35
A method of transmitting a packet of information over a physical link in an Intellectual Property (IP) core interconnect network, the packet including a header and a sequence of one or more payload words, the method comprising:
- transmitting the header and a first payload word over the physical link in a first clock cycle;
- and
- if the payload includes a second payload word, transmitting the second payload word over the physical link in a second clock cycle,
- wherein the physical link includes a number of physical data wires, the number of physical data wires equal to at least a sum of a header width and a payload word width.
A method of defining a packet format for transmission over a physical link of an Intellectual Property (IP) core interconnect network, the method comprising:
- defining a packet including a header and a payload having one or more payload words;
- and
- defining at least two independent parameters, where the combination of the independent parameters control a width of the physical link and a latency to transport the header over the physical link, where the header latency is in addition to a minimal latency to transport the payload over the physical link.
A method of defining a packet format for transmission over a physical link of an Intellectual Property (IP) core interconnect network, the method comprising:
- defining a packet including a header and a payload having one or more payload words;
- and
- defining at least two independent parameters, where the combination of the independent parameters controls a width of the payload and a latency to transport the header over the physical link, where the header latency is in addition to a minimal latency to transport the payload over the physical link.
An Intellectual Property (IP) core interconnect network operable for transmitting a packet including a header and a payload having one or more payload words, the network comprising:
- a physical link including a number of physical data wires, the number of physical data wires equal to at least a sum of a header width and a payload word width;
- a transmitter coupled to the physical link, the transmitter configured for transmitting the header and a first payload word over the physical link during a first clock cycle, if the payload includes a second payload word, transmitting the second payload word over the physical link in a second clock cycle;
- and
- a receiver coupled to the physical link, the receiver configured for receiving the header and the payload.
An Intellectual Property (IP) core interconnect network operable for transmitting a packet format including a header and a payload having one or more payload words, the network comprising:
- a physical link including a number of physical data wires;
- a transmitter coupled to the physical link, the transmitter configured for transmitting a packet having the packet format;
- and
- a receiver coupled to the physical link and configured to receive the transmitted packet,
- where the packet is transmitted based on a combination of independent parameters available to the network for controlling a width of the physical link and a latency to transport the header over the physical link, where the header latency is in addition to a minimal latency to transport the payload over the physical link.
An Intellectual Property (IP) core interconnect network operable for transmitting a packet having a packet format including a header and a sequence of one or more payload words, the network comprising:
- a physical link including a number of physical data wires;
- a transmitter coupled to the physical link, the transmitter configured for transmitting a packet having the packet format;
- and
- a receiver coupled to the physical link and configured to receive the packet,
- where the packet is transmitted based a combination of independent parameters available to the network for controlling a width of the payload and a latency to transport the header over the physical link, where the header latency is in addition to a minimal latency to transport the payload over the physical link.
A system for defining a packet format for an Intellectual Property (IP) core interconnect network, the system comprising:
- an interface;
- and
- a processor coupled to the interface, the processor operable for defining a packet including a header and a payload having one or more payload words, and for receiving through the interface values for at least two independent parameters for controlling a width of a physical link of the network and a latency to transport the header over the physical link, where the header latency is in addition to a minimal latency to transport the payload over the physical link.
A system for defining a packet format for an Intellectual Property (IP) core interconnect network, the system comprising:
- an interface;
- and
- a processor coupled to the interface, the processor operable for defining a packet including a header and a payload having one or more payload words, and for receiving through the interface values for at least two independent parameters for controlling a width of the payload and a latency to transport the header over the physical link, where the header latency is in addition to a minimal latency to transport the payload over the physical link.
Dependencies are inferred from the claim text.