Semiconductor memory device having advanced tag block
OwnerSang-Hoon Hong, Jin-Hong Ahn +2inventors
InventorsSang-Hoon Hong, Jin-Hong Ahn, Jae-Bum Ko, Se-Jun Kim
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Abstract
A semiconductor memory device includes a row decoding block for decoding an inputted address to thereby generate a logical unit cell block address and a decoded word line address; a tag block for converting the logical unit cell block address into a physical unit cell block address; a decoded address latching block for latching the decoded word line address to thereby output the decoded word line address as a word line activation signal in response to the physical unit cell block; and a cell area for outputting a data, which is stored therein, in response to the word line activation signal.
Claims14
A semiconductor memory device, comprising:
- a row decoding block configured to decode a row address, and to output a decoded word line address and a logical cell block address for accessing one of N number of cell blocks;
- a tag block configured to receive the row address, the logical cell block address, and to convert the logical cell block address into a physical cell block address for accessing one of N+1 number of cell blocks;
- an address latching block configured to latch the decoded word line address to output a word line activation signal as a latched word line in response to the physical cell block address;
- a cell area configured to output data in response to the word line activation signal;
- and
- a control unit configured to control the tag block, the row decoding block and a predetermined cell block table, which activates one word line of a cell block selected from the plurality of cell blocks by the physical cell block address.
An operation method of a semiconductor memory device, comprising:
- decoding a row address and outputting a decoded word line address and a logical cell block address for accessing one of N number of cell blocks;
- activating a physical cell block address for accessing one of N+1 number of cell blocks based on a tag memory in response to a decoded row address;
- selecting a latch in response to the decoded row address activating a select word line based on a selected latch in an activated physical cell block;
- and
- accessing data corresponding to an activated word line.
Dependencies are inferred from the claim text.