Semiconductor memory device and information processing system including the same
AssigneeElpida Memory, Inc.
InventorHideyuki Yoko
Life of this patent
Estimating the term…
Abstract
The semiconductor memory device includes plural core chips that are allocated with different chip identification information from each other and an interface chip that controls the plural core chips. The interface chip receives address information to specify memory cells and commonly supplies a part of the address information as chip selection information for comparison with the chip identification information to the plural core chips. As a result, since the controller recognizes that an address space is simply enlarged, the same interface as that in the semiconductor memory device according to the related art can be used.
Claims23
A semiconductor device comprising:
- a plurality of core chips that include a memory cell array having a plurality of memory cells, respectively being assigned a plurality of chip identification information, respectively, and the plurality of chip identification information being different from each other;
- and
- an interface chip that controls the plurality of core chips by using chip selection information that is compared with the chip identification information,
- wherein the interface chip receives address information from outside to specify at least one of the memory cells included in the memory cell array and commonly supplies the plurality of core chips with a part of the address information as the chip selection information.
The semiconductor device as claimed in 2, wherein the control logic circuit is activated, regardless of the chip selection information, when valid command information with respect to all of the plurality of core chips among the command information is supplied.
A semiconductor device mounted on a substrate, comprising:
- an interface chip mounted on the substrate, receiving a plurality of address signals from the substrate, generating chip select information in response to at least one of the address signals;
- a first core chip mounted on the interface chip, holding first chip identification information, receiving the chip select information, comparing the first chip identification information with the chip select information, and outputting a first activate signal when the first chip identification information is coincident with the chip select information;
- and
- a second core chip mounted on the first core chip, holding second chip identification information which is different from the first chip identification information, receiving the chip select information in common with the first core chip, comparing the second chip identification information with the chip select information, and outputting a second activate signal when the second chip identification information is coincident with the chip select information.
Dependencies are inferred from the claim text.