Semiconductor memory device and information processing system including the same
AssigneeElpida Memory, Inc.
InventorNaohisa Nishioka
Life of this patent
Estimating the term…
Abstract
The semiconductor memory device includes plural core chips that are allocated with different chip identification information from each other and an interface chip that controls the plural core chips. A bit number of external unit data that is simultaneously input and output between an external device and the interface chip changes in the interface chip, and the interface chip changes chip selection information for comparison with the chip identification information, according to the bit number of the external unit data. As a result, the page configuration does not need to be changed, when the I/O configuration is changed.
Claims20
A semiconductor device comprising:
- a plurality of core chips assigned different chip identification information from each other;
- and
- an interface chip that controls the core chips by using chip selection information that is compared with the chip identification information, wherein
- the interface chip simultaneously outputs or inputs external unit data comprising a plurality of bits to/from outside, and
- the chip selection information is variable according to a number of bits of the external unit data.
An information processing system comprising:
- a semiconductor memory devices that has a plurality of core chips, each of which has a memory cell array and is assigned different chip identification information, and an interface chip that controls the plurality of core chips by using chip selection information that is compared with the chip identification information;
- and
- a controller that controls the semiconductor memory device, wherein
- the interface chip simultaneously outputs or inputs external unit data comprising a plurality of bits to/from the controller, and
- the chip selection information is variable according to the number of bits of the external unit data.
A semiconductor device comprising:
- a plurality of core chips each holding chip identification information, the chip identification information in each of the core chips being unique among the core chips, each of the core chips including:
- a layer address selecting circuit which receives address information and selects one part of the address information;
- a chip information comparing circuit comparing the one part of the address information with the chip identification information;
- and
- a control logic circuit receiving command information, being activated in response to the command information when the address information is coincident with the chip identification information, and being inactivated in response to the command information when the address information is incoincident with the chip identification information;
- and
- an interface chip sending the address and command information to the core chips in common, and controlling the layer address selecting circuit in each of the core chips to select the one part of the address information.
Dependencies are inferred from the claim text.