Bank re-assignment in chip to reduce ir drop
AssigneeNanya Technology Corporation
InventorsRichard Michael Parent, Ryan Andrew Jurasek, Dave Eugene Chapmen
Life of this patent
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Abstract
A chip system that has reduced power consumption under specific operational modes includes: a DDR3 chip that includes: a plurality of pads, disposed at the centre of the DDR3 chip; and an array of banks, each bank having a specific logical address, surrounding the pads. The chip system further includes: a clock, coupled to the DDR3 chip, for controlling a rate of data transmission; and a memory controller, coupled to the clock, for coordinating transmitted data with relevant processes, and for selectively reassigning the bank logical addresses according to a specific operational mode.
Claims4
A chip system that has reduced power consumption under specific operational modes, comprising:
- a DDR3 chip, comprising:
- a plurality of pads, disposed at the centre of the DDR3 chip;
- and
- an array of banks, each bank having a specific logical address, surrounding the pads;
- a clock, coupled to the DDR3 chip, for controlling a rate of data transmission;
- and
- a memory controller, coupled to the clock, for coordinating transmitted data with relevant processes, and for selectively reassigning the bank logical addresses according to a specific operational mode.
A method for reducing power consumption in a chip under specific operational modes, the method comprising:
- providing a DDR3 chip, comprising:
- a plurality of pads, disposed at the centre of the DDR3 chip;
- and
- an array of banks, each bank having a specific logical address, surrounding the pads;
- providing a clock, for controlling a rate of data transmission for the DDR3 chip;
- and
- providing a memory controller for coordinating transmitted data with relevant processes of the DDR3 chip, and for selectively reassigning the bank logical addresses according to a specific operational mode.
Dependencies are inferred from the claim text.