Method for Extending Word-Line Pulses

An integrated circuit comprising:

• a positive power supply node;
• a first plurality of PMOS transistors coupled in series and coupled to the positive power supply node, wherein gates of the plurality of PMOS transistors are interconnected;
• a plurality of diodes coupled between the plurality of PMOS transistors and an electrical ground;
• a charging node;
• a second plurality of PMOS transistors configured to form current mirrors with each other, wherein each of the second plurality of PMOS transistors is coupled between the positive power supply node and the charging node;
• a third plurality of PMOS transistors, each coupled between one of the second plurality of PMOS transistors and the charging node, wherein a gate of each of the third plurality of PMOS transistors is connected to a drain of one of the first plurality of PMOS transistors;
• and
• a PMOS transistor forming current mirrors with the second plurality of PMOS transistors, wherein a drain of the PMOS transistor is directly connected to the charging node.

An integrated circuit comprising:

• a positive power supply node;
• a charging node;
• a clock pulse node;
• a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor coupled in series and between the positive power supply node and an electrical ground, wherein gates of the first PMOS transistor and the second PMOS transistor are interconnected, and a gate and a drain of each of the first NMOS transistor and the second NMOS transistor are interconnected;
• a third PMOS transistor and a fourth PMOS transistor coupled in series and between the positive power supply node and the charging node, wherein a gate of the fourth PMOS transistor is coupled to a drain of the first PMOS transistor;
• a fifth PMOS transistor and a sixth PMOS transistor coupled in series and between the positive power supply node and the charging node, wherein a gate of the sixth PMOS transistor is coupled to a drain of the second PMOS transistor;
• a seventh PMOS transistor coupled between the positive power supply node and the charging node, wherein a drain of the seventh PMOS transistor is directly connected to the charging node;
• a current tracking circuit;
• and
• an eighth PMOS transistor configured to share a same current with the current tracking circuit, wherein gates of the third, the fifth, the seventh, and the eighth PMOS transistors are interconnected.