Semiconductor device and information processing system including the same

An information processing system comprising:

• a semiconductor device including a plurality of core chips and an interface chip that supplies each of the plurality of core chips with an associated bit of non-used chip signals;
• and
• a controller that controls the semiconductor device, wherein
• each of the core chips includes:
• a chip address generating circuit that receives a first chip address and generates a second chip address to identify the corresponding core chip based on received first chip address;
• and
• a chip address comparing circuit that compares a third chip address supplied from the interface chip and the second chip address, wherein
• the chip address generating circuit supplies the first chip address that has different value of the received first chip address to another core chip when the non-used chip signal is in an inactivated state,
• the chip address generating circuit supplies the first chip address that has same value of the received first chip address to another core chip when the non-used chip signal is in an activated state,
• the chip address comparing circuit activates a chip selection signal when the third chip address and the second chip address are matched with each other,
• the chip address comparing circuit inactivates the chip selection signal regardless of the third chip address when the non-used chip signal is in the activated state, and
• the controller supplies the third chip address to the interface chip.

A semiconductor device comprising:

• a plurality of first chips each including a chip address generating circuit that generates a chip address and a chip address comparing circuit that compare the chip address and a chip selection information;
• and
• a second chip supplying the chip selection information to the first chips in common and supplying each bit of non-used chip signals to an associated one of the first chips, wherein
• the chip address generating circuits generate the chip addresses having different value from one another when corresponding bits of the non-used chip signals are in an inactive state, and
• the chip address comparing circuits are inactivated when corresponding bits of non-used chip signals are in an active state.