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US 2011/0085395 A1Published application
Output enable signal generating circuit and method of semiconductor memory apparatus
AssigneeHynix Semiconductor Inc.
InventorHyeng Ouk Lee
Life of this patent
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Abstract
An output enable signal generating circuit for a semiconductor memory apparatus includes an output control unit configured to receive CAS latency information and to generate an output control signal having enable timing according to a DLL on/off mode, and an output enable signal output unit configured to receive the output control signal and to output an output enable signal in response to a read command and a DLL clock signal.
Claims6
An output enable signal generating circuit for a semiconductor memory apparatus, the circuit comprising:
- a DLL off delay control unit configured to generate a DLL off output delay signal in response to CAS latency delay signal;
- a switching unit configured to output the DLL off output delay signal as an output control signal in a DLL off mode;
- and
- an output enable signal output unit configured to receive the output control signal and to output an output enable signal in response to a read command and a DLL clock signal.
1 more element
Dependencies are inferred from the claim text.