Latency circuit and semiconductor device comprising same

A latency circuit comprising:

• a latency control block that generates a plurality of even first control clocks, a plurality of odd first control clocks, and a second control clock using a plurality of divided signals each having a period twice as long as a period of an external clock;
• an internal read command generator that generates an even internal read command and an odd internal read command based on a sampling operation on the second control clock using a decoded read command;
• and
• a latency signal generation unit that generates a latency signal based on a shifting operation on the even internal read command and the odd internal read command using the plurality of even first control clocks and the plurality of odd first control clocks.

A semiconductor memory device comprising:

• a memory cell array comprising a plurality of memory cells;
• a data output buffer that receives output data from the memory cell array;
• and
• a latency circuit that generates a latency signal for the data output buffer, the latency circuit comprising:
• a latency control block that generates a plurality of first control clocks by delaying a delay sync signal generated based on an external clock, and generates a second control clock having a predetermined margin with respect to a read command decoded based on the delay sync signal;
• an internal read command generator that samples the second control clock using the decoded read command and generates an internal read command based on a sampled second control clock;
• and
• a latency signal generation unit that generates the latency signal based on a shifting operation performed on the internal read command using the plurality of first control clocks.