Word-line level shift circuit

An SRAM device, comprising:

• a plurality of word-line level shifter circuits for shifting word-line select signals from a lower voltage to a higher voltage, wherein each word-line level shifter circuit comprises:
• a first transistor gated by a word-line select input that is driven at the lower voltage, a second transistor gated by a restore input that is driven at the higher voltage, and a third transistor that is gated by a and word-line decode input, wherein the first, second and third transistors are coupled along a series path to a source at the higher voltage;
• a control node along the series path that is driven to ground upon activation of the word-line select input and the word-line decode input, and is driven to the higher voltage upon activation of the restore input;
• an output node that is driven to the higher voltage in response to the control node being at ground and is driven to ground in response to the control node being at the higher voltage;
• and
• a feedback circuit that maintains the control node at the higher voltage in response to the word-line select input being de-activated;
• and
• a shared level shifter that generates the restore input for each of the plurality of word-line level shifter circuits.

A level shifter circuit for shifting a data signal from a lower voltage to a higher voltage, comprising:

• a first transistor gated by a data input at the lower voltage, and a second transistor gated by a restore input at the higher voltage, wherein the first and second transistors are coupled along a series path to a source at the higher voltage;
• a control node along the series path;
• an output node coupled to the control node via a first pair of driver transistors;
• and
• a feedback circuit having a second pair of parallel transistors and a feedback transistor, wherein the feedback transistor couples the second pair of parallel transistors to the control node and is gated by the output node.