Method and system to lower the minimum operating voltage of a memory array
AssigneeIntel Corporation
InventorsMuhammad M. Khellah, Bibiche M. Geuskens, Arijit Raychowdhury
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Abstract
A method and system to lower the minimum operating voltage of a memory array during read and/or write operations of the memory array. In one embodiment of the invention, the voltage of the read and/or write word line of the memory array is boosted or increased during read and/or write operations of the memory array. By doing so, the NMOS devices in the memory array are strengthened and the contention between the NMOS and PMOS devices are reduced during read and/or write operations of the memory array. This helps to lower or reduce the required VCCmin of the memory array during read and/or write operations of the memory array.
Claims17
An apparatus comprising:
- a charge pump circuit to provide a first voltage and a second voltage, wherein the second voltage is higher than the first voltage;
- and
- a two stage level shifter (2SLS) circuit coupled with the charge pump circuit to:
- provide the second voltage to a word line of a memory array responsive to an access operation of the memory array.
A system comprising:
- a memory array having a read word line and a write word line;
- and
- a module coupled with the read word line and the write word line to:
- set a voltage boosting level of the read word line and write word line;
- and
- provide a boosted voltage to the read word line and write word line based on the voltage boosting level.
A method comprising:
- providing a first voltage and a second voltage to a bit line and a complementary bit line of a plurality of memory cells respectively, wherein the first voltage is equal to the second voltage;
- performing a write operation to each memory cell;
- determining that more than half of the plurality of memory cells are not written successfully;
- incrementing a count in response to the determination;
- decreasing the second voltage based at least in part on the count;
- and
- repeating the steps of performing, determining, incrementing, and decreasing until a determination that less than half of the plurality of memory cells are not written successfully.
Dependencies are inferred from the claim text.