Universal dual charge-retaining transistor flash NOR cell, a dual charge-retaining transistor flash NOR cell array, and method for operating same

Abstract

A NOR flash memory cell is formed of dual serially connected charge retaining transistors. A drain/source of a first of the dual charge retaining transistors connected to a local bit line and a source/drain of a second of the dual charge retaining transistors connected to a local source line. The drain/sources of the commonly connected dual serially connected charge retaining transistors are connected solely together. The drain/sources and source drains are formed in a diffusion well. In some embodiments, the diffusion well is formed in a deep diffusion well. The dual serially connected charge retaining transistors are N-channel or P-channel charge retaining transistors with the charge retaining layers being either floating gate or SONOS charge trapping layers. Selected charge retaining transistors are programmed by a combination of a band-to-band tunneling and a Fowler-Nordheim tunneling and erased by a Fowler Nordheim tunneling.

Dependencies are inferred from the claim text.