US 2011/0085378 A1Published application

Memory and Operation Method Therefor

AssigneeMacronix International Co., Ltd.

InventorsHsin-Yi Ho, Chun-Hsiung Hung, Yun-Chen Chou

Life of this patent

Estimating the term…

Loading patent…

Abstract

In an operation method for a memory including a plurality of memory cells, a first reading is performed on the memory cells by applying a reference voltage; the reference voltage is moved if it is checked that the first reading result is not correct; a second reading is performed on the memory cells by applying the moved reference voltage; a first total number of a first logic state in the first reading is compared with a second total number of the first logic state in the second reading if it is checked that the second reading result is not correct; and the moving of the reference voltage is stopped if the first reading result has the same number of the first logic state as the second reading result, and the moved reference voltage is stored as a target reference voltage.

Claims14

Dependent claims

An operation method for a memory including a plurality of memory cells, comprising steps of:

performing a first reading operation on the memory cells by applying a reference voltage;
checking if a first total number of a first logic state in the first reading operation is correct or not;
moving the reference voltage if the first total number of the first logic state in the first reading operation is not correct;
performing a second reading operation on the memory cells by applying the moved reference voltage;
checking if a second total number of the first logic state in the second reading operation is correct or not;
comparing the first total number of the first logic state in the first reading operation with the second total number of the first logic state in the second reading operation if the second total number of the first logic state in the second reading operation is not correct;
and
stopping the moving the reference voltage step if the first total number of the first logic state in the first reading operation is the same as the second total number of the first logic state in the second reading operation, and storing the moved reference voltage as a target reference voltage.

5 more elements

A memory including:

a memory array including a plurality of memory cells;
and
a read control circuit, coupled to the memory array, the read control circuit controlling reading operation on the memory array;
wherein
in a first reading operation, the memory cells are read by applying a reference voltage;
the read control circuit checks if a first total number of a first logic state in the first reading operation is correct or not;
the read control circuit moves the reference voltage if the first total number of the first logic state in the first reading operation is not correct;
in a second reading operation, the memory cells are read by applying the moved reference voltage;
the read control circuit checks if a second total number of the first logic state in the second reading operation is correct or not;
the read control circuit compares the first total number of the first logic state in the first reading operation with the second total number of the first logic state in the second reading operation if the second total number of the first logic state in the second reading operation is not correct;
and
the read control circuit stops movement of the reference voltage if the first total number of the first logic state in the first reading operation is the same as the second total number of the first logic state in the second reading operation, and stores the moved reference voltage as a target reference voltage.

9 more elements

Dependencies are inferred from the claim text.