# US 2011/0084960 A1 · Shift register and display device

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- Number: US 2011/0084960 A1
- Document ID: US20110084960A1
- Status: Published application
- Kind: A1
- Application number: 12/897,375
- Filed: 2010-10-04
- Published: 2011-04-14
- Earliest claimed: 2009-10-09
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Hiroyuki Miyake; Seiko Amano
- Web page: https://patentgrep.com/patent/US20110084960A1

## CPC

- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- G09G 3/3266: Details of drivers for scan electrodes
- G09G 3/3677: {suitable for active matrices only}
- G09G 2300/0408: Integration of the drivers onto the display substrate
- G09G 2300/0417: Special arrangements specific to the use of low carrier mobility technology
- G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
- G09G 2320/0223: Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
- G09G 2320/0285: using tables for spatial correction of display data
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

The shift register includes first to fourth flip-flops. A first clock signal which is in a first voltage state in a first period and in a second voltage state in second to fourth periods is input to the first flip-flop. A second clock signal which is in the first voltage state in the second period and in the second voltage state in the third period and the fourth period is input to the second flip-flop. A third clock signal which is in the second voltage state in the first, second, and fourth periods and in the first voltage state in the third period is input to the third flip-flop. A fourth clock signal which is in the second voltage state in the first and second periods and in the first voltage state in the fourth period is input to the fourth flip-flop.

## Claims

### Claim 1

A shift register comprising:
a first flip-flop to which a first clock signal which is in a first voltage state in a first period and in a second voltage state in second to fourth periods is input;
a second flip-flop to which a second clock signal which is in the first voltage state in at least part of the second period and in the second voltage state in at least part of the third period, and the fourth period is input;
a third flip-flop to which a third clock signal which is in the second voltage state in the first, second, and fourth periods and in the first voltage state in the third period is input; and
a fourth flip-flop to which a fourth clock signal which is in the second voltage state in at least part of the first period, and the second period and in the first voltage state in at least part of the fourth period is input.

### Claim 2 (depends on 1)

The shift register according to claim 1, further comprising:
a first clock signal line to which the first clock signal is input;
a second clock signal line to which the second clock signal is input;
a third clock signal line to which the third clock signal is input;
a fourth clock signal line to which the fourth clock signal is input;
a first power supply line to which a high power supply voltage is applied; and
a second power supply line to which a low power supply voltage is applied,
wherein each of the first to fourth flip-flops comprises:
a first transistor comprising:
a gate;
a source; and
a drain,
wherein a start signal is input to the gate, and
wherein one of the source and the drain is electrically connected to the first power supply line;
a second transistor comprising:
a gate;
a source; and
a drain,
wherein the gate is electrically connected to the other of the source and the drain of the first transistor,
wherein one of the source and the drain is electrically connected to one of the first to fourth clock signal lines, and
wherein an output signal is output from the other of the source and the drain; and
a third transistor comprising:
a gate;
a source; and
a drain,
wherein one of the source and the drain is electrically connected to the gate of the second transistor, and
wherein the other of the source and the drain is electrically connected to the second power supply line.

### Claim 3 (depends on 2)

The shift register according to claim 2, wherein the first to third transistors have a same conductivity type.

### Claim 4 (depends on 2, 3)

The shift register according to claim 2 or claim 3, wherein each of the first to third transistors comprises an oxide semiconductor layer serving as a channel formation layer.

### Claim 5 (depends on 1, 2, 3, 4)

A display device comprising:
a driver circuit comprising the shift register according to any one of claims 1 to 4; and
a pixel portion comprising a pixel whose display state is controlled by the driver circuit.

### Claim 6

A method for driving a shift register comprising a first to fourth flip-flops, comprising:
inputting a first clock signal, which is in a first voltage state in a first period and in a second voltage state in second to fourth periods, to the first flip-flop;
inputting a second clock signal, which is in the first voltage state in at least part of the second period and in the second voltage state in at least part of the third period, and the fourth period, to the second flip-flop;
inputting a third clock signal, which is in the second voltage state in the first, second, and fourth periods and in the first voltage state in the third period, to the third flip-flop; and
inputting a fourth clock signal, which is in the second voltage state in at least part of the first period, and the second period and in the first voltage state in at least part of the fourth period, to the fourth flip-flop.