Apparatus and method for pipelined analog to digital conversion

An apparatus comprising:

• a pipelined analog-to-digital converter comprising a control and correction circuit;
• and
• a plurality of multiplying digital-to-analog converter (MDAC) stages coupled in cascade to one another, wherein at least one of the MDAC stages comprises:
• an MDAC input configured to receive an analog input voltage;
• and
• a dual latch flash analog-to-digital ADC comprising one or more dual latch comparators, at least one of the dual latch comparators comprising:
• a pre-amplifier having an input coupled to the MDAC input, and an output;
• a demultiplexer having an input coupled to the output of the pre-amplifier, a first output, and a second output;
• a first latch having an input coupled to the first output of the demultiplexer, wherein the first latch is configured to generate a first digital signal;
• and
• a second latch having an input coupled to the second output of the demultiplexer, wherein the second latch is configured to generate a second digital signal,
• wherein the first latch and the second latch alternate analog-to-digital conversion in response to control from the control and correction circuit,
• wherein the at least one of the MDAC stages further comprises:
• a delay circuit configured to delay the analog input voltage to generate a delayed input voltage;
• a capacitor block configured to sample and hold the delayed input voltage, the capacitor block being further configured to subtract a reference voltage from the delayed input voltage to generate a residue signal;
• and
• an amplifier configured to amplify the residue signal.

An apparatus comprising:

• a pipelined analog-to-digital converter comprising a control and correction circuit;
• and
• a plurality of multiplying digital-to-analog converter (MDAC) stages coupled in cascade to one another, wherein at least one of the MDAC stages comprises:
• an MDAC input configured to receive an analog input voltage;
• and
• a dual latch flash analog-to-digital converter (ADC) comprising one or more dual latch comparators, at least one of the dual latch comparators comprising:
• a pre-amplifier having an input coupled to the MDAC input, and an output;
• a demultiplexer having an input coupled to the output of the pre-amplifier, a first output, and a second output;
• a first latch having an input coupled to the first output of the demultiplexer, wherein the first latch is configured to generate a first digital signal;
• and
• a second latch having an input coupled to the second output of the demultiplexer, wherein the second latch is configured to generate a second digital signal,
• wherein the first latch and the second latch alternate analog-to-digital conversion in response to control from the control and correction circuit,
• wherein the at least one of the MDAC stages further comprises:
• a first capacitor block configured to sample and hold the input voltage, the first capacitor block being further configured to subtract a reference voltage from the input voltage in response to the first digital signal to generate a first residue signal;
• a second capacitor block configured to sample and hold the input voltage, the second capacitor block being further configured to subtract a reference voltage from the input voltage in response to the second digital signal to generate a second residue signal;
• and
• an amplifier configured to alternately amplify the first and second residue signals.

An apparatus comprising:

• a pipelined analog-to-digital converter comprising a control and correction circuit;
• and
• a plurality of multiplying digital-to-analog converter (MDAC) stages coupled in cascade to one another, wherein at least one of the MDAC stages comprises:
• an MDAC input configured to receive an analog input voltage;
• and
• a dual latch flash analog-to-digital converter (ADC) comprising one or more dual latch comparators, at least one of the dual latch comparators comprising:
• a pre-amplifier having an input coupled to the MDAC input, and an output;
• a demultiplexer having an input coupled to the output of the pre-amplifier, a first output, and a second output;
• a first latch having an input coupled to the first output of the demultiplexer, wherein the first latch is configured to generate a first digital signal;
• and
• a second latch having an input coupled to the second output of the demultiplexer, wherein the second latch is configured to generate a second digital signal,
• wherein the first latch and the second latch alternate analog-to-digital conversion in response to control from the control and correction circuit,
• wherein the at least one of the MDAC stages further comprises:
• a first capacitor block configured to sample and hold the input voltage, the first capacitor block being further configured to subtract a reference voltage from the input voltage in response to one of the first and second digital signals to generate a first residue signal;
• a second capacitor block configured to sample and hold the input voltage, the second capacitor block being further configured to subtract a reference voltage from the input voltage in response to one of the first and second digital signals to generate a second residue signal;
• and
• a third capacitor block configured to sample and hold the input voltage, the third capacitor block being further configured to subtract a reference voltage from the input voltage in response to one of the first and second digital signals to generate a third residue signal.

An apparatus comprising:

• a pipelined analog-to-digital converter comprising a control and correction circuit;
• and
• a plurality of multiplying digital-to-analog converter (MDAC) stages coupled in cascade to one another, wherein at least one of the MDAC stages comprises:
• an MDAC input configured to receive an analog input voltage;
• and
• a dual latch flash analog-to-digital converter (ADC) comprising one or more dual latch comparators, at least one of the dual latch comparators comprising:
• a pre-amplifier having an input coupled to the MDAC input, and an output;
• a demultiplexer having an input coupled to the output of the pre-amplifier, a first output, and a second output;
• a first latch having an input coupled to the first output of the demultiplexer, wherein the first latch is configured to generate a first digital signal;
• and
• a second latch having an input coupled to the second output of the demultiplexer, wherein the second latch is configured to generate a second digital signal,
• wherein the first latch and the second latch alternate analog-to-digital conversion in response to control from the control and correction circuit,
• wherein the demultiplexer further has a third output, wherein the at least one of the dual latch comparators further comprises a third latch having an input coupled to the third output of the demultiplexer, wherein the third latch is configured to generate a third digital signal, and wherein the first latch, the second latch, and the third latch alternate analog-to-digital, conversion in response to control from the control and correction circuit.

An apparatus comprising:

• a pipelined analog-to-digital converter comprising a control and correction circuit;
• and
• a plurality of multiplying digital-to-analog converter (MDAC) stages coupled in cascade to one another, wherein at least one of the MDAC stages comprises:
• an MDAC input configured to receive an analog input voltage;
• and
• a dual latch flash analog-to-digital (ADC) comprising one or more dual latch comparators, at least one of the dual latch comparators comprising:
• a pre-amplifier having an input coupled to the MDAC input, and an output;
• a demultiplexer having an input coupled to the output of the pre-amplifier, a first output, and a second output;
• a first latch having an input coupled to the first output of the demultiplexer, wherein the first latch is configured to generate a first digital signal;
• and
• a second latch having an input coupled to the second output of the demultiplexer, wherein the second latch is configured to generate a second digital signal,
• wherein the first latch and the second latch alternate analog-to-digital conversion in response to control from the control and correction circuit,
• wherein the at least one of the MDAC stages further comprises:
• a third latch configured to receive and latch the first digital signal from the first latch, and to output a first latched digital signal;
• and
• a fourth latch configured to receive and latch the second digital signal from the second latch, and to output a second latched digital signal,
• wherein the at least one of the MDAC stages further comprises:
• a first capacitor block configured to sample and hold the input voltage, the first capacitor block being further configured to subtract a reference voltage from the input voltage in response to one of the first and second latched digital signals to generate a first residue signal;
• a second capacitor block configured to sample and hold the input voltage, the second capacitor block being further configured to subtract a reference voltage from the input voltage in response to one of the first and second latched digital signals to generate a second residue signal;
• a third capacitor block configured to sample and hold the input voltage, the third capacitor block being further configured to subtract a reference voltage from the input voltage in response to one of the first and second latched digital signals to generate a third residue signal;
• and
• a fourth capacitor block configured to sample and hold the input voltage, the fourth capacitor block being further configured to subtract a reference voltage from the input voltage in response to one of the first and second latched digital signals to generate a fourth residue signal.

A method for pipelined analog-to-digital conversion, the method comprising:

• converting a first analog signal into a digital signal;
• converting the digital signal into a second analog signal;
• subtracting the second analog signal from the first analog signal, thereby generating a residue signal;
• and
• amplifying the residue signal;
• wherein converting the first analog signal comprises:
• pre-amplifying, by a pre-amplifier of a flash ADC, the first analog signal and a reference voltage to generate a pre-amplified first analog signal and a pre-amplified reference voltage;
• providing, by a demultiplexer having a first output and a second output, the pre-amplified first analog signal and the pre-amplified reference voltage alternately via the first output or the second output;
• comparing, by a first comparator latch of the flash ADC, the pre-amplified first analog signal with the pre-amplified reference voltage to generate a first digital signal during at least part of a first phase or cycle of a clock signal;
• and
• comparing, by a second comparator latch of the flash ADC, the pre-amplified first analog signal with the pre-amplified reference voltage to generate a second digital signal during at least part of a second phase or cycle of a clock signal immediately subsequent to the first phase or cycle.

A method for pipelined analog-to-digital conversion, the method comprising:

• converting a first analog signal into a digital signal;
• converting the digital signal into a second analog signal;
• subtracting the second analog signal from the first analog signal, thereby generating a residue signal;
• and
• amplifying signal;
• wherein converting the first analog signal comprises:
• pre-amplifying, by a pre-amplifier of a flash ADC, the first analog signal and a reference voltage;
• comparing, by a first comparator latch of the flash ADC, the pre-amplified first analog signal with the pre-amplified reference voltage to generate a first digital signal during at least part of a first phase or cycle of a clock signal;
• and
• comparing, by a second comparator latch of the flash ADC, the pre-amplified first analog signal with the pre-amplified reference voltage to generate a second digital signal during at least part of a second phase or cycle of a clock signal immediately subsequent to the first phase or cycle;
• wherein the method further comprises delaying the first analog signal, and wherein converting the digital signal into the second analog signal comprises converting the delayed first analog signal into the second analog signal.

A method for pipelined analog-to-digital conversion, the method comprising:

• converting a first analog signal into a digital signal;
• converting the digital signal into a second analog signal;
• subtracting the second analog signal from the first analog signal, thereby generating a residue signal;
• and
• amplifying the residue signal;
• wherein converting the first analog signal comprises:
• pre-amplifying, by a pre-amplifier of a flash ADC, the first analog signal and a reference voltage;
• comparing, by a first comparator latch of the flash ADC, the pre-amplified first analog signal with the pre-amplified reference voltage to generate a first digital signal during at least part of a first phase or cycle of a clock signal;
• and
• comparing, by a second comparator latch of the flash ADC, the pre-amplified first analog signal with the pre-amplified reference voltage to generate a second digital signal during at least part of a second phase or cycle of a clock signal immediately subsequent to the first phase or cycle,
• wherein converting the digital signal into the second analog signal comprises:
• connecting a first capacitor block to a first reference voltage at least partly in response to the first digital signal during at least part of the first phase or cycle of the clock signal;
• and
• connecting a second capacitor block to a second reference voltage at least partly in response to the second digital signal during at least part of the second phase or cycle of the clock signal.

A method for pipelined analog-to-digital conversion, the method comprising:

• converting a first analog signal into a digital signal;
• converting the digital signal into a second analog signal;
• subtracting the second analog signal from the first analog signal, thereby generating a residue signal;
• and
• amplifying the residue signal;
• wherein converting the first analog signal comprises:
• pre-amplifying, by a pre-amplifier of a flash ADC, the first analog signal and a reference voltage;
• comparing, by a first comparator latch of the flash ADC, the pre-amplified first analog signal with the pre-amplified reference voltage to generate a first digital signal during at least part of a first phase or cycle of a clock signal;
• and
• comparing, by a second comparator latch of the flash ADC, the pre-amplified first analog signal with the pre-amplified reference voltage to generate a second digital signal during at least part of a second phase or cycle of a clock signal immediately subsequent to the first phase or cycle,
• wherein the method further comprises:
• selecting one of three or more capacitor blocks;
• and
• randomly selecting another of the three or more capacitor blocks,
• wherein converting the digital signal into the second analog signal comprises:
• connecting the selected capacitor block to a first reference voltage at least partly in response to the first digital signal;
• and
• connecting the other randomly selected capacitor block to a second reference voltage at least partly in response to the second digital signal.

A method for pipelined analog-to-digital conversion, the method comprising:

• converting a first analog signal into a digital signal;
• converting the digital signal into a second analog signal;
• subtracting the second analog signal from the first analog signal, thereby generating a residue signal;
• and
• amplifying the residue signal;
• wherein converting the first analog signal comprises:
• pre-amplifying, by a pre-amplifier of a flash ADC, the first analog signal and a reference voltage;
• comparing, by a first comparator latch of the flash ADC, the pre-amplified first analog signal with the pre-amplified reference voltage to generate a first digital signal during at least part of a first phase or cycle of a clock signal;
• and
• comparing, by a second comparator latch of the flash ADC, the pre-amplified first analog signal with the pre-amplified reference voltage to generate a second digital signal during at least part of a second phase or cycle of a clock signal immediately subsequent to the first phase or cycle,
• wherein converting the first analog signal further comprises:
• comparing, by a third comparator latch of the flash ADC, the pre-amplified first analog signal with the pre-amplified reference voltage to generate a third digital signal during at least part of a third phase or cycle of a clock signal immediately subsequent to the second phase or cycle.

A method for pipelined analog-to-digital conversion, the method comprising:

• converting a first analog signal into a digital signal;
• converting the digital signal into a second analog signal;
• subtracting the second analog signal from the first analog signal, thereby generating a residue signal;
• and
• amplifying the residue signal;
• wherein converting the first analog signal comprises:
• pre-amplifying, by a pre-amplifier of a flash ADC, the first analog signal and a reference voltage;
• comparing, by a first comparator latch of the flash ADC, the pre-amplified first analog signal with the pre-amplified reference voltage to generate a first digital signal during at least part of a first phase or cycle of a clock signal;
• and
• comparing, by a second comparator latch of the flash ADC, the pre-amplified first analog signal with the pre-amplified reference voltage to generate a second digital signal during at least part of a second phase or cycle of a clock signal immediately subsequent to the first phase or cycle,
• wherein the method further comprises latching, by a first latch external to the flash ADC, the first digital signal to generate a first latched digital signal during at least part of the second phase or cycle;
• and
• latching, by a second latch external to the flash ADC, the second digital signal to generate a second latched digital signal during at least part of a third phase or cycle of the clock signal immediately subsequent to the second phase or cycle,
• wherein converting the first analog signal further comprises:
• comparing, by the first comparator latch of the flash ADC, the pre-amplified first analog signal with the pre-amplified reference voltage to generate a third digital signal during at least part of the third phase or cycle of a clock signal;
• and
• latching, by the first latch external to the flash ADC, the third digital signal to generate a third latched digital signal during at least part of a fourth phase or cycle of the clock signal immediately subsequent to the third phase or cycle.