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US 2011/0084775 A1Published application
Resonant clock distribution network architecture for tracking parameter variations in conventional clock distribution networks
AssigneeCyclos Semiconductor, Inc.
InventorsMarios C. Papaefthymiou, Alexander Ishii
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Abstract
A resonant clock distribution network architecture is proposed that enables a resonant clock network to track the impact of parameter variations on the insertion delay of a conventional clock distribution network, thus limiting clock skew between the two networks and yielding increased performance. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.
Claims1
A clock distribution network, comprising:
- a conventional clock distribution network including a plurality of buffers configured to propagate a reference clock signal;
- a resonant clock distribution network including a resonant clock driver having a drive element electrically coupled to a clock node of the resonant clock driver, the drive element configured to receive and propagate a reference clock signal, a programmable delay electrically coupled between a reference clock input and the drive element;
- and
- a buffer network electrically coupled between the reference clock input to the resonant clock distribution network and the drive element of the resonant clock driver, wherein the buffer network mirrors a topology and loading of a sub-network of the conventional clock distribution network.
1 more element
Dependencies are inferred from the claim text.