Architecture for single-stepping in resonant clock distribution networks
AssigneeCyclos Semiconductor, Inc.
InventorsMarios C. Papaefthymiou, Alexander Ishii
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Abstract
A resonant clock distribution network architecture is proposed that is capable of single-step operation through the use of selective control in the resonant clock drivers and the deployment of flip-flops that require the clock to remain stable for a sufficiently long time between any two consecutive state updates. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.
Claims1
A clock driver that can selectively be operated in a resonant mode or a non-resonant mode, the clock driver comprising:
- a resonance element electrically coupled to a clock node of the clock driver, the resonance element configured to enable the clock driver to operate in a resonant mode;
- a drive element electrically coupled to the clock node, the drive element configured to receive and propagate a reference clock of the clock distribution network based on a logical input signal, wherein the logical input signal is a logical combination of the reference clock and a control signal, wherein the drive element is enabled for operation when the control signal is in an active state;
- a clocking element electrically coupled to the clock node, the clocking element gated by a gating signal;
- wherein, the clock driver selectively operates in a resonant mode or in a non-resonant mode based on the values of the control signal and the gating signal, wherein:
- the clock driver operates in a resonant mode when the control signal is in an active state and the gating signal is an inactive state, wherein the clock driver operates at a frequency relative to a natural resonating frequency of the resonance element;
- the clock driver operates in a non-resonant mode when the control signal is in an inactive state and the gating signal is in an active state, wherein the clock driver operates at a frequency relative to a gating frequency of the gating signal.
Dependencies are inferred from the claim text.