Three Dimensional Inductor and Transformer

A three dimensional on-chip transformer comprising:

• a first on-chip inductor and a second on-chip inductor, each of the first and second on-chip inductors comprising
• a plurality of first segments in a first metal layer;
• a plurality of second segments in a second metal layer;
• a first inductor input and a second inductor input, the first and second inductor inputs being located in one of the first metal layer and the second metal layer;
• and
• a plurality of through silicon vias coupling the plurality of first segments and the plurality of second segments to form a continuous, non-intersecting path between the first inductor input and the second inductor input;
• the first on-chip inductor being inductively coupled to the second on-chip inductor, and the first on-chip inductor not being physically coupled to the second on-chip inductor except through ground.

A three dimensional on-chip radio frequency amplifier comprising:

• a first on-chip transformer comprising a first on-chip inductor and a second on-chip inductor;
• a second on-chip transformer comprising a third on-chip inductor and a fourth on-chip inductor;
• a first on-chip transistor comprising a gate, a drain and a source;
• wherein each of the first, second, third and fourth on-chip inductors comprises a plurality of first segments in a first metal layer;
• a plurality of second segments in a second metal layer;
• a first inductor input and a second inductor input, the first and second inductor inputs being located in one of the first metal layer and the second metal layer;
• and a plurality of through silicon vias coupling the plurality of first segments and the plurality of second segments to form a continuous, non-intersecting path between the first inductor input and the second inductor input;
• the first on-chip inductor being inductively coupled to the second on-chip inductor, the third on-chip inductor being inductively coupled to the fourth on-chip inductor, and the first, second, third and fourth on-chip inductors not being physically coupled to one another except through ground;
• the first inductor input of the first on-chip inductor being coupled to an input of the on-chip radio frequency amplifier;
• the first inductor input of the second on-chip inductor being coupled to the gate of the first on-chip transistor;
• the first inductor input of the third on-chip inductor being coupled to the drain of the first on-chip transistor, the first inductor input of the fourth on-chip inductor being coupled to an output of the on-chip radio frequency amplifier;
• the second inductor input of the first, second, third and fourth on-chip inductors being coupled to ground;
• and the source of the first on-chip transistor being coupled to ground.

A three dimensional on-chip electronic device comprising:

• a first on-chip inductor comprising a first plurality of first layer segments in a first metal layer, a first plurality of second layer segments in a second metal layer, a first inductor input and a first inductor output, and a first plurality of through silicon vias coupling the first plurality of first layer segments and the first plurality of second layer segments to form a continuous, non-intersecting path between the first inductor input and the first inductor output, the first inductor input and the first inductor output being located in one of the first metal layer and the second metal layer, the first inductor output being coupled to ground;
• and
• a second on-chip inductor comprising a second plurality of first layer segments in the first metal layer, a second plurality of second layer segments in the second metal layer, a second inductor input and a second inductor output, and a second plurality of through silicon vias coupling the second plurality of first layer segments and the second plurality of second layer segments to form a continuous, non-intersecting path between the second inductor input and the second inductor output, the second inductor input and the second inductor output being located in one of the first metal layer and the second metal layer, the second inductor output being coupled to ground;
• the first on-chip inductor being inductively coupled to the second on-chip inductor, and the first on-chip inductor not being physically coupled to the second on-chip inductor except through ground.