Flip-flop with single clock phase and with reduced dynamic power
AssigneeSTMicroelectronics S.r.l.
InventorsFabian Firmin, Sylvain Clerc, Jean-Pierre Schoellkopf, Fady Abouzeid
Life of this patent
Estimating the term…
Abstract
A flip-flop may include a first master stage for latching data, a second slave stage for latching data, and an input multiplexer circuit receiving, as input, data to be latched in the flip-flop. The multiplexer may have single clock phase. The first master stage may be clocked based upon a clock phase, whereas the second stage may be clocked based upon another clock phase.
Claims22
1-9. (canceled)
A flip-flop device comprising:
- a first master stage configured to latch data;
- a second slave stage configured to latch data;
- and
- a multiplexing circuit configured to receive, as input, data to be latched;
- said multiplexing circuit configured to be clocked by a clock signal;
- said first master stage configured to be clocked based upon a first type phase of the clock signal;
- said second slave stage configured to be clocked based upon a second type of phase of the clock signal.
A flip-flop device comprising:
- a first master stage configured to latch data and comprising a first latching memory having an input, and a first inverter coupled at the input of the first latching memory;
- a second slave stage configured to latch data and comprising a second latching memory having an input, and second and third inverters coupled series at the input of the second latching memory;
- and
- a multiplexing circuit configured to receive, as input, data to be latched;
- said multiplexing circuit configured to be clocked by a clock signal;
- said first master stage configured to be clocked based upon a first type of phase of the clock signal;
- said second slave stage configured to be clocked based upon a second type of phase of the clock signal.
A method of operating a flip-flop device comprising a first master stage configured to latch data, a second slave stage configured to latch data, and a multiplexing circuit configured to receive, as input, data to be latched, the method comprising:
- clocking the multiplexing circuit with a clock signal;
- clocking the first master stage based upon a first type of phase of the clock signal;
- and
- clocking the second slave stage based upon a second type of phase of the clock signal.
Dependencies are inferred from the claim text.