Output buffer with slew-rate enhancement output stage

An output buffer with a slew-rate enhancement output stage, comprising:

• an operational amplifier comprising a positive input terminal for receiving an input voltage, a negative input terminal for receiving an output voltage, and an output terminal for outputting the output voltage;
• a first PMOS transistor comprising a first first terminal coupled to a high voltage source, a first control terminal coupled to a first node inside the operational amplifier, and a first second terminal coupled to the output terminal of the operational amplifier;
• a first NMOS transistor comprising a second first terminal coupled the output terminal of the operational amplifier, a second control terminal coupled to a second node inside the operational amplifier, and a second second terminal coupled to a low voltage source;
• a first slew-rate enhancement circuit coupled to the first node and outputting a first voltage;
• a second slew-rate enhancement circuit coupled to the second node and outputting a second voltage;
• a second PMOS transistor comprising a third first terminal coupled to the high voltage source, a third control terminal for receiving the first voltage, and a third second terminal coupled to the output terminal of the operational amplifier;
• and
• a second NMOS transistor comprising a fourth first terminal coupled to the output terminal of the operational amplifier, a fourth control terminal for receiving the second voltage, and a fourth second terminal coupled to the low voltage source.