Phase locked loop and voltage controlled oscillator thereof

A phase locked loop (PLL), comprising:

• a phase detector, for comparing a phase of an input reference clock signal with a phase of an output clock signal so as to output a control signal accordingly;
• a charge pump, coupled to the phase detector, for generating an output voltage in response to the control signal;
• a loop filter, coupled to the charge pump, for filtering high frequency noises on the output voltage;
• and
• a voltage controlled oscillator (VCO), comprising:
• a ring oscillator circuit, for providing an output clock signal;
• and
• a control circuit, coupled to the ring oscillator circuit, for receiving an output voltage to respectively provide a first voltage-frequency gain and a second voltage-frequency gain so as to control a frequency of the output clock signal provided by the ring oscillator circuit, wherein the first voltage-frequency gain is larger than the second voltage-frequency gain.