Power-on reset circuit
AssigneeOki Semiconductor Co., Ltd.
InventorYukio Kawamura
Life of this patent
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Abstract
A power-on reset circuit includes a first-conductive-type MOS transistor having a first source connected to a first power supply, a first drain, and a first gate connected to a second power supply; a second-conductive-type MOS transistor having a second source connected to the second power supply, a second drain connected to the first drain, and a second gate, to which a bias potential which depends on neither a potential of the first power supply nor a potential of the second power supply is applied; and an output node for outputting a reset signal corresponding to a potential of the first drain, in a process that a voltage between the first power supply and the second power supply increases.
Claims12
A power-on reset circuit comprising:
- a first-conductive-type MOS transistor having a first source connected to a first power supply, a first drain, and a first gate connected to a second power supply;
- a second-conductive-type MOS transistor having a second source connected to the second power supply, a second drain connected to the first drain, and a second gate, to which a bias potential which depends on neither a potential of the first power supply nor a potential of the second power supply is applied;
- and
- an output node for outputting a reset signal corresponding to a potential of the first drain, in a process that a voltage between the first power supply and the second power supply increases.
A power-on reset circuit comprising:
- a first sensor circuit;
- a second sensor circuit;
- and
- a reset signal generating circuit for generating a reset signal;
- wherein the first sensor circuit has:
- a first first-conductive-type MOS transistor which has a first source connected to a first power supply, a first drain, and a first gate connected to a second power supply;
- a first second-conductive-type MOS transistor which has a second source connected to the second power supply, a second drain connected to the first drain, and a second gate to which a bias potential is applied;
- and
- a first node which outputs a first signal corresponding to a potential of the first drain, in a process that a voltage between the first power supply and the second power supply increases;
- wherein the second sensor circuit has:
- a second first-conductive-type MOS transistor which has a third source connected to the first power supply, a third drain, and a third gate connected to the second power supply;
- a second second-conductive-type MOS transistor which has a fourth source connected to the second power supply, a fourth drain connected to the third drain, and a fourth gate to which the bias potential is applied;
- and
- a second node which outputs a second signal corresponding to a potential of the third drain at timing occurring after timing of outputting the first signal from the first node, in the process that the voltage between the first power supply and the second power supply increases;
- and
- wherein the reset signal generating circuit generates the reset signal from the first signal and the second signal.
Dependencies are inferred from the claim text.