Architecture for controlling clock characteristics
AssigneeCyclos Semiconductor, Inc.
InventorsMarios C. Papaefthymiou, Alexander Ishii
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Abstract
An architecture for controlling the clock waveform characteristics, including but not limited to the clock amplitude and clock rise and/or fall times, of resonant clock distribution networks is proposed. This architecture relies on controlling the size of clock drivers and the duty cycles of reference clocks. It is targeted at resonant clock distribution networks and allows for the adjustment of resonant clock waveform characteristics with no need to route an additional power grid. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.
Claims20
A clock driver of a clock distribution network for generating a resultant clock signal to be supplied to a circuit block, the clock driver comprising:
- a plurality of drive elements electrically coupled to a clock node of the resonant clock driver, each of the plurality of drive elements configured to receive and propagate a reference clock of the clock distribution network;
- and
- a pre-adjustment module operably coupled between the inputs of the plurality of drive elements and a signal generator that generates the reference clock, the pre-adjustment module configured to adjust a duty cycle of the reference clock supplied to the plurality of drive elements so as to control a final value of an amplitude, a rise time, and/or a fall time of the resultant signal.
A clock distribution network for an integrated circuit, the clock distribution network comprising:
- a signal generator configured to generate a reference clock;
- a plurality of clock drivers, each of the plurality of clock drivers configured to receive the reference clock and generate a resultant clock signal to be supplied to a particular circuit block of the integrated circuit;
- and
- a plurality of pre-adjustment modules, each of the plurality of pre-adjustment modules operably coupled between the signal generator and one of the plurality of clock drivers, the pre-adjustment module associated with a given clock driver configured to adjust a duty cycle of the reference clock supplied to the given clock driver so as to control a final value of an amplitude, a rise time, and/or a fall time of the resultant signal generated by the given clock driver.
A method of operation of a clock driver of a clock distribution network, the method comprising:
- electrically coupling a plurality of drive elements electrically to a clock node of the resonant clock driver, each of the plurality of drive elements configured to receive and propagate a reference clock of the clock distribution network;
- operably coupling a pre-adjustment module between the inputs of the plurality of drive elements and a signal generator that generates the reference clock;
- and
- using the pre-adjustment module, selectively adjusting a duty cycle of the reference clock supplied to the plurality of drive elements so as to control a final value of an amplitude, a rise time, and/or a fall time of the resultant signal.
Dependencies are inferred from the claim text.